Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T77,T82,T83	Yes	T75,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T83,T255,T256	Yes	T83,T255,T256	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T4,T100,T101	Yes	T4,T100,T101	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T98,T100	Yes	T4,T98,T100	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T7,T80,T81	Yes	T7,T80,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T212,T76,T133	Yes	T212,T76,T133	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T212,T75,T76	Yes	T212,T75,T76	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T4,T63,T64	Yes	T4,T63,T64	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T47,T7,T198	Yes	T47,T7,T198	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T47,T7,T198	Yes	T47,T7,T198	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T47,T7,T198	Yes	T47,T7,T198	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T47,T7,T198	Yes	T47,T7,T198	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T47,T7,T198	Yes	T47,T7,T198	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T47,T7,T198	Yes	T47,T7,T198	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T47,*T7,*T198	Yes	T47,T7,T198	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T47,T7,T198	Yes	T47,T7,T198	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T77,T133,T82	Yes	T77,T133,T82	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T76,T77,T133	Yes	T75,T76,T77	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T76,T82,T84	Yes	T76,T82,T84	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T77,T133,T82	Yes	T77,T133,T82	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T77,T82,T83	Yes	T77,T82,T84	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T83	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T77,*T133,*T82	Yes	T77,T133,T82	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T78,T264,T265	Yes	T78,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T78,T264,T265	Yes	T78,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T78,T264,T265	Yes	T78,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T78,T264,T265	Yes	T78,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T78,T264,T265	Yes	T78,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T78,*T264,*T265	Yes	T78,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T78,T264,T265	Yes	T78,T264,T265	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T59,T30	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T78,T264,T265	Yes	T78,T264,T265	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T78,T264,T265	Yes	T78,T264,T265	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T4,T59,T30	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T78,*T264,*T265	Yes	T78,T264,T265	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T4,T59,T30	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T78,T264,T265	Yes	T78,T264,T265	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T5,T44,T47	Yes	T5,T44,T47	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T5,T44,T45	Yes	T5,T44,T45	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T385,T49,T50	Yes	T385,T49,T50	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T385,T49,T50	Yes	T385,T49,T50	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T385,T49,T50	Yes	T385,T49,T50	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T77,*T82,*T84	Yes	T77,T82,T84	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T385,T49,T50	Yes	T385,T49,T50	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T385,T49,T50	Yes	T385,T49,T50	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T76,T77,T82	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T385,T407,T408	Yes	T385,T407,T408	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T133	Yes	T49,T50,T51	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T385,T407,T408	Yes	T385,T49,T50	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T77,*T82,*T83	Yes	T77,T82,T83	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T75,T76,T77	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T408,*T409,*T410	Yes	T385,T407,T408	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T385,T49,T50	Yes	T385,T49,T50	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T7,*T78,*T79	Yes	T7,T78,T79	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T7,T80,T81	Yes	T7,T80,T81	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T94,T98,T100	Yes	T94,T98,T100	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T7,*T78,*T79	Yes	T7,T78,T79	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T77,*T82,*T84	Yes	T77,T82,T84	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T39,T207,T208	Yes	T39,T207,T208	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T77,*T82,*T83	Yes	T77,T82,T83	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T11,*T12,*T161	Yes	T11,T12,T161	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T11,T12,T161	Yes	T11,T12,T161	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T12,T161,T398	Yes	T12,T161,T398	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T12,T161,T13	Yes	T12,T161,T13	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T12,T161,T398	Yes	T12,T161,T398	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T12,T161,T398	Yes	T12,T161,T398	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T12,T161,T13	Yes	T12,T161,T13	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T12,T161,T398	Yes	T12,T161,T398	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T77,*T82,*T84	Yes	T77,T82,T84	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T12,T161,T398	Yes	T12,T161,T398	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T12,T161,T398	Yes	T12,T161,T398	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T75,T76,T77	Yes	T76,T77,T82	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T12,T161,T13	Yes	T12,T161,T13	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T12,T161,T398	Yes	T12,T161,T398	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T12,T161,T13	Yes	T12,T161,T13	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T75,T77,T82	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T77,*T82,*T83	Yes	T75,T77,T82	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T12,*T161,*T398	Yes	T12,T161,T398	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T12,T161,T398	Yes	T12,T161,T398	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T17,T251,T18	Yes	T17,T251,T18	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T17,T251,T18	Yes	T17,T251,T18	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T251,T18	Yes	T17,T251,T18	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T17,T251,T18	Yes	T17,T251,T18	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T17,T251,T18	Yes	T17,T251,T18	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T77,*T82,*T84	Yes	T77,T82,T84	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T17,T251,T18	Yes	T17,T251,T18	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T17,T251,T18	Yes	T17,T251,T18	INPUT
tl_usbdev_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T251,T398,T19	Yes	T251,T398,T19	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T251,T398,T19	Yes	T251,T398,T19	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T17,T251,T18	Yes	T17,T251,T18	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T77,*T82,*T83	Yes	T77,T82,T84	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T17,*T251,*T18	Yes	T17,T251,T18	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T17,T251,T18	Yes	T17,T251,T18	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T59,T30	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T4,T59,T30	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T80,*T75,*T77	Yes	T80,T77,T82	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T80,T77,T82	Yes	T80,T77,T82	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T80,T76,T77	Yes	T80,T75,T76	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T80,T77,T133	Yes	T80,T77,T133	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T80,T77,T82	Yes	T80,T77,T82	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T80,*T77,*T133	Yes	T80,T77,T133	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T59,T30	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T44,T375,T45	Yes	T44,T375,T45	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T375,T45	Yes	T44,T375,T45	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T30,T44,T200	Yes	T30,T44,T200	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T44,T375,T45	Yes	T44,T375,T45	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T30,T44,T200	Yes	T30,T44,T200	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T375,T12,T411	Yes	T375,T12,T411	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T30,T44,T200	Yes	T30,T44,T200	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T30,T44,T200	Yes	T30,T44,T200	INPUT
tl_hmac_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T84	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T44,T200,T375	Yes	T44,T200,T375	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T200,T375	Yes	T44,T200,T375	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T44,T375,T45	Yes	T44,T375,T45	INPUT
tl_hmac_i.d_sink	Yes	Yes	T77,T84,T83	Yes	T75,T77,T84	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T80,*T77,*T83	Yes	T80,T75,T77	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T75,T76,T77	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T44,*T375,*T45	Yes	T44,T375,T45	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T44,T200,T375	Yes	T44,T200,T375	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T12,T118,T161	Yes	T12,T118,T161	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T30,T200,T250	Yes	T30,T200,T250	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T30,T200,T250	Yes	T30,T200,T250	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T12,T118,T161	Yes	T12,T118,T161	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T30,T200,T250	Yes	T30,T200,T250	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T12,T451,T387	Yes	T12,T451,T387	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T30,T200,T250	Yes	T30,T200,T250	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T30,T200,T250	Yes	T30,T200,T250	INPUT
tl_kmac_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T30,T200,T250	Yes	T30,T200,T250	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T200,T250	Yes	T30,T200,T250	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T12,T170,T172	Yes	T12,T172,T161	INPUT
tl_kmac_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T12,*T170,*T172	Yes	T12,T172,T161	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T30,T200,T250	Yes	T30,T200,T250	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T376,T120,T707	Yes	T376,T120,T707	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T376,T120,T707	Yes	T376,T120,T707	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T30,T132,T200	Yes	T30,T132,T200	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T376,T120,T707	Yes	T376,T120,T707	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T30,T132,T200	Yes	T30,T132,T200	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T7,*T212,*T77	Yes	T7,T212,T77	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T30,T132,T200	Yes	T30,T132,T200	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T30,T132,T376	Yes	T30,T132,T376	INPUT
tl_aes_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T30,T132,T376	Yes	T30,T132,T376	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T132,T376,T107	Yes	T132,T376,T107	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T30,T132,T376	Yes	T30,T132,T376	INPUT
tl_aes_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T7,*T212,*T77	Yes	T7,T212,T77	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T30,*T132,*T376	Yes	T30,T132,T376	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T30,T132,T376	Yes	T30,T132,T376	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T130,*T132,*T107	Yes	T130,T44,T132	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T203,T130,T132	Yes	T203,T130,T132	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T7,*T80,*T212	Yes	T7,T80,T212	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T203,T130,T132	Yes	T203,T130,T132	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T77,T82,T83	Yes	T77,T82,T84	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T7,*T80,*T212	Yes	T7,T80,T212	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T203,*T130,*T132	Yes	T203,T130,T132	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T75,T76,T77	Yes	T76,T77,T82	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T77,T82,T83	Yes	T77,T82,T84	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T75,T77	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T130,*T132,*T107	Yes	T130,T132,T107	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	INPUT
tl_edn1_i.d_error	Yes	Yes	T75,T76,T77	Yes	T76,T77,T82	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	INPUT
tl_edn1_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T76,T77,T82	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T130,*T132,*T107	Yes	T130,T132,T107	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T130,T132,T107	Yes	T130,T132,T107	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T3,T4,T91	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T77,*T82,*T84	Yes	T77,T82,T84	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T77,*T82,*T84	Yes	T77,T82,T84	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T91	Yes	T3,T4,T91	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T4,T91	Yes	T3,T4,T91	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T130,T44,T132	Yes	T130,T44,T132	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T30,T130,T44	Yes	T30,T130,T44	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T30,T130,T44	Yes	T30,T130,T44	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T130,T44,T132	Yes	T130,T44,T132	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T30,T130,T44	Yes	T30,T130,T44	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T81,*T210,*T211	Yes	T81,T210,T211	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T30,T130,T44	Yes	T30,T130,T44	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T30,T130,T44	Yes	T30,T130,T44	INPUT
tl_otbn_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T130,T44,T132	Yes	T130,T44,T132	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T130,T44	Yes	T30,T130,T44	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T30,T130,T44	Yes	T30,T130,T44	INPUT
tl_otbn_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T81,*T210,*T211	Yes	T81,T210,T211	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T130,*T44,*T132	Yes	T130,T44,T132	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T30,T130,T44	Yes	T30,T130,T44	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_keymgr_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T44,T172,T223	Yes	T44,T172,T223	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T80,*T77,*T82	Yes	T80,T77,T82	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T76,T77,T84	Yes	T76,T77,T82	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T44,*T45,*T46	Yes	T44,T45,T46	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T78,*T77,*T82	Yes	T78,T77,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T77,T133,T82	Yes	T77,T133,T82	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T59	Yes	T3,T4,T59	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T3,T4,T59	Yes	T3,T4,T59	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T77,*T82,*T83	Yes	T78,T77,T82	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T443,*T444,*T77	Yes	T443,T444,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T133	Yes	T76,T77,T133	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T160,T305,T306	Yes	T160,T305,T306	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T160,T41,T42	Yes	T44,T45,T46	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T160,T41,T42	Yes	T44,T45,T46	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T77,*T82,*T83	Yes	T443,T444,T77	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T160,*T185,*T305	Yes	T160,T247,T445	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T59,T30	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T75,T77,T82	Yes	T75,T77,T82	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range