Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3661970	1			T79	75		T80	114		T81	1352
values[2]	731587	1			T79	36		T80	52		T81	138
values[3]	102393	1			T79	5		T80	5		T81	3
values[4]	54590	1			T412	12		T137	39		T521	1
values[5]	36856	1			T412	12		T137	19		T391	261
values[6]	27341	1			T412	12		T137	12		T391	219
values[7]	21695	1			T412	12		T137	13		T391	163
values[8]	18516	1			T412	12		T137	16		T391	137
values[9]	16447	1			T412	13		T137	10		T391	101
values[10]	14835	1			T412	12		T137	10		T391	76
values[11]	13735	1			T412	12		T137	5		T391	76
values[12]	12908	1			T412	12		T137	2		T391	79
values[13]	12122	1			T412	12		T137	3		T391	93
values[14]	11418	1			T412	12		T137	3		T391	77
values[15]	10686	1			T412	12		T137	2		T391	61
values[16]	10754	1			T412	12		T137	1		T391	66
values[17]	10415	1			T412	13		T137	2		T391	56
values[18]	10051	1			T412	13		T137	2		T391	52
values[19]	9401	1			T412	13		T137	4		T391	51
values[20]	8944	1			T412	13		T137	1		T391	42
values[21]	8893	1			T412	12		T137	2		T391	24
values[22]	8855	1			T412	12		T137	1		T391	21
values[23]	8641	1			T412	12		T137	1		T391	24
values[24]	8351	1			T412	12		T137	2		T391	30
values[25]	7775	1			T412	12		T137	1		T391	43
values[26]	7605	1			T412	12		T137	1		T391	52
values[27]	7469	1			T412	12		T137	1		T391	41
values[28]	7151	1			T412	12		T137	3		T391	46
values[29]	6638	1			T412	13		T137	4		T391	36
values[30]	6251	1			T412	12		T137	1		T391	30
values[31]	5791	1			T412	13		T137	3		T391	26
values[32]	5345	1			T412	12		T137	3		T391	22
values[33]	4941	1			T412	13		T137	8		T391	27
values[34]	4643	1			T412	12		T137	4		T391	17
values[35]	4350	1			T412	12		T137	1		T391	37
values[36]	3881	1			T412	12		T137	2		T391	34
values[37]	3760	1			T412	12		T391	29		T519	5
values[38]	3579	1			T412	12		T391	24		T519	5
values[39]	3500	1			T412	12		T391	25		T519	6
values[40]	3401	1			T412	12		T391	22		T519	6
values[41]	3350	1			T412	13		T391	18		T519	5
values[42]	3282	1			T412	12		T391	19		T519	6
values[43]	3237	1			T412	12		T391	16		T519	5
values[44]	3048	1			T412	12		T391	20		T519	5
values[45]	3031	1			T412	12		T391	17		T519	5
values[46]	2985	1			T412	12		T391	30		T519	6
values[47]	2865	1			T412	12		T391	21		T519	5
values[48]	2903	1			T412	12		T391	21		T519	5
values[49]	2891	1			T412	12		T391	28		T519	5
values[50]	2811	1			T412	13		T391	26		T519	5
values[51]	2695	1			T412	12		T391	15		T519	5
values[52]	2678	1			T412	13		T391	26		T519	5
values[53]	2616	1			T412	12		T391	20		T519	5
values[54]	2560	1			T412	12		T391	13		T519	5
values[55]	2528	1			T412	12		T391	18		T519	5
values[56]	2439	1			T412	12		T391	26		T519	5
values[57]	2399	1			T412	12		T391	20		T519	5
values[58]	2352	1			T412	12		T391	20		T519	5
values[59]	2300	1			T412	13		T391	15		T519	5
values[60]	2395	1			T412	12		T391	15		T519	6
values[61]	2658	1			T412	12		T391	23		T519	6
values[62]	3828	1			T412	12		T391	51		T519	5
values[63]	10713	1			T412	14		T391	138		T519	5
values[64]	216483	1			T412	2240		T391	580		T519	856

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4663851	1			T79	112		T80	113		T81	1208
values[2]	789646	1			T79	30		T80	29		T81	85
values[3]	83335	1			T79	4		T80	6		T81	8
values[4]	14682	1			T80	1		T412	47		T137	24
values[5]	5455	1			T412	16		T137	14		T482	1
values[6]	3279	1			T412	5		T137	20		T391	68
values[7]	2463	1			T412	5		T137	22		T391	45
values[8]	2151	1			T412	4		T137	20		T391	50
values[9]	1892	1			T412	4		T137	17		T391	28
values[10]	1641	1			T412	5		T137	15		T391	17
values[11]	1582	1			T412	4		T137	7		T391	12
values[12]	1507	1			T412	4		T137	13		T391	18
values[13]	1364	1			T412	4		T137	10		T391	11
values[14]	1198	1			T412	4		T137	14		T391	16
values[15]	1096	1			T412	4		T137	21		T391	8
values[16]	1080	1			T412	4		T137	25		T391	8
values[17]	961	1			T412	4		T137	22		T391	9
values[18]	960	1			T412	4		T137	21		T391	4
values[19]	985	1			T412	4		T137	10		T391	4
values[20]	999	1			T412	4		T137	7		T391	6
values[21]	802	1			T412	4		T391	3		T516	4
values[22]	782	1			T412	4		T391	3		T516	10
values[23]	739	1			T412	4		T391	5		T516	4
values[24]	669	1			T412	4		T391	9		T516	3
values[25]	659	1			T412	4		T391	8		T516	5
values[26]	733	1			T412	4		T391	9		T516	8
values[27]	731	1			T412	4		T391	16		T516	11
values[28]	671	1			T412	4		T391	14		T516	11
values[29]	590	1			T412	4		T391	15		T516	9
values[30]	522	1			T412	4		T391	5		T516	9
values[31]	546	1			T412	4		T391	6		T516	4
values[32]	557	1			T412	4		T391	3		T516	2
values[33]	552	1			T412	4		T391	6		T516	3
values[34]	595	1			T412	4		T391	11		T516	3
values[35]	593	1			T412	4		T391	9		T516	7
values[36]	564	1			T412	4		T391	11		T516	10
values[37]	538	1			T412	4		T391	13		T516	8
values[38]	529	1			T412	4		T391	16		T516	5
values[39]	468	1			T412	4		T391	8		T516	6
values[40]	464	1			T412	5		T391	15		T516	5
values[41]	461	1			T412	4		T391	12		T516	5
values[42]	462	1			T412	5		T391	12		T516	3
values[43]	472	1			T412	4		T391	11		T516	3
values[44]	437	1			T412	4		T391	6		T516	3
values[45]	454	1			T412	4		T391	6		T516	5
values[46]	454	1			T412	4		T391	2		T516	3
values[47]	440	1			T412	4		T516	12		T517	5
values[48]	424	1			T412	4		T516	7		T517	2
values[49]	407	1			T412	4		T516	3		T517	1
values[50]	400	1			T412	4		T516	3		T517	1
values[51]	389	1			T412	4		T516	3		T517	3
values[52]	384	1			T412	4		T516	6		T517	1
values[53]	363	1			T412	4		T516	5		T517	1
values[54]	379	1			T412	4		T516	6		T517	3
values[55]	367	1			T412	4		T516	4		T517	2
values[56]	385	1			T412	4		T516	2		T517	2
values[57]	347	1			T412	4		T516	5		T517	1
values[58]	384	1			T412	4		T516	6		T517	1
values[59]	347	1			T412	4		T516	9		T517	5
values[60]	376	1			T412	4		T516	4		T517	2
values[61]	381	1			T412	4		T516	2		T517	2
values[62]	663	1			T412	4		T516	10		T517	2
values[63]	2574	1			T412	4		T516	48		T517	10
values[64]	24361	1			T412	658		T516	92		T517	151

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	557705	1			T79	2		T80	1		T81	180
values[2]	2598352	1			T79	75		T80	110		T81	883
values[3]	1160654	1			T79	77		T80	77		T81	254
values[4]	149240	1			T79	3		T80	2		T81	4
values[5]	77611	1			T80	1		T412	12		T137	48
values[6]	49992	1			T412	12		T137	38		T391	808
values[7]	35303	1			T412	12		T137	43		T391	508
values[8]	27621	1			T412	12		T137	41		T391	398
values[9]	23199	1			T412	12		T137	55		T391	280
values[10]	19909	1			T412	12		T137	44		T391	234
values[11]	17914	1			T412	12		T137	37		T391	251
values[12]	16764	1			T412	12		T137	36		T391	221
values[13]	15348	1			T412	12		T137	41		T391	180
values[14]	14293	1			T412	13		T137	36		T391	116
values[15]	13606	1			T412	12		T137	36		T391	118
values[16]	13127	1			T412	12		T137	54		T391	116
values[17]	12702	1			T412	12		T137	53		T391	126
values[18]	11917	1			T412	12		T137	56		T391	127
values[19]	11827	1			T412	12		T137	39		T391	146
values[20]	11322	1			T412	12		T137	24		T391	122
values[21]	10565	1			T412	12		T137	8		T391	101
values[22]	10170	1			T412	12		T137	8		T391	94
values[23]	9650	1			T412	12		T137	3		T391	70
values[24]	9497	1			T412	12		T137	6		T391	52
values[25]	9073	1			T412	12		T391	61		T519	5
values[26]	8537	1			T412	12		T391	59		T519	5
values[27]	8315	1			T412	12		T391	57		T519	6
values[28]	7899	1			T412	12		T391	68		T519	5
values[29]	7361	1			T412	12		T391	56		T519	5
values[30]	7068	1			T412	12		T391	35		T519	5
values[31]	6555	1			T412	12		T391	45		T519	5
values[32]	5908	1			T412	12		T391	42		T519	5
values[33]	5607	1			T412	12		T391	46		T519	5
values[34]	5150	1			T412	12		T391	58		T519	5
values[35]	4784	1			T412	12		T391	42		T519	5
values[36]	4677	1			T412	12		T391	41		T519	5
values[37]	4410	1			T412	12		T391	37		T519	5
values[38]	3995	1			T412	12		T391	46		T519	5
values[39]	4047	1			T412	12		T391	34		T519	6
values[40]	3950	1			T412	12		T391	29		T519	5
values[41]	3796	1			T412	12		T391	38		T519	5
values[42]	3779	1			T412	12		T391	37		T519	5
values[43]	3574	1			T412	12		T391	32		T519	5
values[44]	3470	1			T412	12		T391	44		T519	5
values[45]	3334	1			T412	12		T391	33		T519	5
values[46]	3313	1			T412	12		T391	26		T519	5
values[47]	3278	1			T412	13		T391	16		T519	5
values[48]	3344	1			T412	12		T391	17		T519	5
values[49]	3298	1			T412	12		T391	30		T519	5
values[50]	3197	1			T412	12		T391	25		T519	5
values[51]	3148	1			T412	12		T391	23		T519	5
values[52]	3054	1			T412	12		T391	16		T519	5
values[53]	3045	1			T412	13		T391	23		T519	5
values[54]	2955	1			T412	12		T391	16		T519	5
values[55]	2884	1			T412	14		T391	17		T519	5
values[56]	2851	1			T412	12		T391	22		T519	5
values[57]	2761	1			T412	13		T391	20		T519	5
values[58]	2745	1			T412	12		T391	14		T519	5
values[59]	2740	1			T412	12		T391	19		T519	5
values[60]	2743	1			T412	12		T391	24		T519	5
values[61]	2805	1			T412	12		T391	21		T519	5
values[62]	3690	1			T412	12		T391	28		T519	5
values[63]	9414	1			T412	13		T391	63		T519	6
values[64]	208819	1			T412	2273		T391	288		T519	888