Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1754194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37268004

1

T1

6888

T2

22155

T3

18062

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26991786	1			T1	3018		T2	12162		T3	13737
values[0x0]	10567078	1			T1	3870		T2	9993		T3	4325
values[0x1]	1463334	1			T1	379		T2	501		T3	3855

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	510404	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38511794

1

T1

7267

T2

22656

T3

21917

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18482867	1			T1	3634		T2	11328		T3	10959
valid_sources[0x01]	18482464	1			T1	3633		T2	11328		T3	10958
valid_sources[0x02]	33429	1			T201	1		T366	160		T152	795
valid_sources[0x03]	33511	1			T366	195		T152	781		T377	658
valid_sources[0x04]	33467	1			T200	2		T201	2		T366	165
valid_sources[0x05]	32585	1			T200	3		T366	184		T152	840
valid_sources[0x06]	33884	1			T366	173		T152	870		T377	592
valid_sources[0x07]	32454	1			T366	168		T152	786		T377	604
valid_sources[0x08]	32476	1			T366	188		T152	737		T377	603
valid_sources[0x09]	32640	1			T366	170		T152	797		T377	645
valid_sources[0x0a]	33053	1			T84	1		T201	2		T366	171
valid_sources[0x0b]	33436	1			T201	1		T366	163		T152	769
valid_sources[0x0c]	32937	1			T201	1		T366	176		T152	795
valid_sources[0x0d]	32738	1			T200	3		T366	157		T152	713
valid_sources[0x0e]	33455	1			T84	1		T53	39		T366	167
valid_sources[0x0f]	32661	1			T83	1		T84	3		T201	1
valid_sources[0x10]	35926	1			T366	171		T152	775		T377	661
valid_sources[0x11]	33228	1			T201	1		T366	164		T152	772
valid_sources[0x12]	33043	1			T200	5		T201	1		T366	166
valid_sources[0x13]	33227	1			T201	1		T366	161		T152	727
valid_sources[0x14]	32892	1			T83	2		T200	1		T201	1
valid_sources[0x15]	34650	1			T84	3		T201	1		T366	180
valid_sources[0x16]	33102	1			T83	3		T201	1		T366	177
valid_sources[0x17]	32552	1			T83	2		T366	159		T152	799
valid_sources[0x18]	32797	1			T200	4		T366	171		T152	789
valid_sources[0x19]	33291	1			T83	2		T366	168		T152	800
valid_sources[0x1a]	32779	1			T83	1		T366	145		T152	856
valid_sources[0x1b]	33251	1			T83	1		T201	1		T366	176
valid_sources[0x1c]	33413	1			T60	39		T366	173		T152	794
valid_sources[0x1d]	32798	1			T200	2		T201	1		T366	160
valid_sources[0x1e]	32712	1			T201	2		T366	170		T152	771
valid_sources[0x1f]	32967	1			T83	3		T84	1		T201	2
valid_sources[0x20]	32867	1			T83	2		T200	4		T366	136

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26474847

1

T1

3018

T2

12162

T3

13737

values[0x0]

all_enables

biggest_size

10511598

1

T1

3870

T2

9993

T3

4325

values[0x1]

all_enables

biggest_size

281559

1

T60

22

T83

24

T84

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2775650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

437707

1

T79

14

T80

22

T81

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1088925	1			T79	39		T80	51		T81	30
values[0x0]	1036053	1			T79	37		T80	49		T81	4
values[0x1]	1088379	1			T79	40		T80	71		T81	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2149239	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1064118

1

T79

31

T80

52

T81

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50725	1			T80	4		T81	3		T85	31
valid_sources[0x01]	50479	1			T80	1		T85	26		T412	41
valid_sources[0x02]	50526	1			T79	3		T80	4		T85	40
valid_sources[0x03]	50510	1			T80	4		T81	1		T85	14
valid_sources[0x04]	50067	1			T80	2		T85	9		T412	45
valid_sources[0x05]	50679	1			T80	1		T81	2		T85	4
valid_sources[0x06]	50580	1			T79	8		T80	6		T85	6
valid_sources[0x07]	49781	1			T81	1		T85	2		T412	44
valid_sources[0x08]	49684	1			T80	1		T81	1		T85	16
valid_sources[0x09]	50043	1			T80	5		T85	2		T412	53
valid_sources[0x0a]	50412	1			T79	9		T80	3		T81	1
valid_sources[0x0b]	50573	1			T80	1		T81	4		T85	20
valid_sources[0x0c]	49827	1			T79	1		T80	2		T81	1
valid_sources[0x0d]	49271	1			T80	6		T81	2		T85	4
valid_sources[0x0e]	50184	1			T80	2		T81	2		T85	30
valid_sources[0x0f]	50220	1			T80	2		T81	3		T85	11
valid_sources[0x10]	48917	1			T80	3		T81	2		T85	5
valid_sources[0x11]	50842	1			T79	2		T80	1		T85	10
valid_sources[0x12]	50801	1			T80	2		T81	2		T85	6
valid_sources[0x13]	50482	1			T80	6		T81	2		T85	12
valid_sources[0x14]	50420	1			T79	4		T81	1		T85	35
valid_sources[0x15]	50682	1			T80	2		T81	3		T85	1
valid_sources[0x16]	50401	1			T80	3		T85	7		T412	37
valid_sources[0x17]	49250	1			T79	21		T80	4		T85	13
valid_sources[0x18]	49490	1			T79	5		T80	5		T81	1
valid_sources[0x19]	49793	1			T80	4		T81	3		T85	17
valid_sources[0x1a]	49705	1			T80	3		T85	13		T412	37
valid_sources[0x1b]	49890	1			T79	5		T80	6		T85	12
valid_sources[0x1c]	50533	1			T79	1		T80	1		T81	1
valid_sources[0x1d]	50035	1			T85	12		T412	46		T137	10
valid_sources[0x1e]	50768	1			T80	3		T81	1		T85	14
valid_sources[0x1f]	50816	1			T79	1		T80	1		T81	1
valid_sources[0x20]	50353	1			T85	16		T412	53		T137	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45972

1

T79

2

T80

3

T85

20

values[0x0]

all_enables

biggest_size

345610

1

T79

12

T80

16

T81

1

values[0x1]

all_enables

biggest_size

46125

1

T80

3

T81

3

T85

11

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2973354	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

482934

1

T79

14

T80

15

T81

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1183470	1			T79	41		T80	53		T81	18
values[0x0]	1089984	1			T79	50		T80	40		T81	5
values[0x1]	1182834	1			T79	55		T80	56		T81	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2282217	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1174071

1

T79

48

T80

47

T81

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55069	1			T79	2		T81	1		T85	28
valid_sources[0x01]	53990	1			T85	15		T412	49		T137	5
valid_sources[0x02]	53150	1			T79	5		T80	3		T81	1
valid_sources[0x03]	53982	1			T81	2		T85	44		T412	46
valid_sources[0x04]	54416	1			T81	1		T85	17		T412	40
valid_sources[0x05]	53494	1			T80	1		T85	7		T412	65
valid_sources[0x06]	53385	1			T81	1		T85	4		T412	43
valid_sources[0x07]	53647	1			T80	2		T412	58		T137	17
valid_sources[0x08]	53963	1			T79	4		T80	18		T81	1
valid_sources[0x09]	53763	1			T80	2		T85	19		T412	44
valid_sources[0x0a]	53878	1			T79	8		T85	9		T412	41
valid_sources[0x0b]	54566	1			T79	4		T81	2		T85	2
valid_sources[0x0c]	53870	1			T79	4		T81	1		T85	5
valid_sources[0x0d]	53932	1			T79	7		T81	1		T85	18
valid_sources[0x0e]	54493	1			T81	1		T85	9		T412	41
valid_sources[0x0f]	54310	1			T79	4		T80	3		T81	1
valid_sources[0x10]	53525	1			T79	4		T80	2		T81	1
valid_sources[0x11]	53712	1			T79	7		T85	4		T412	51
valid_sources[0x12]	53370	1			T79	1		T80	5		T81	2
valid_sources[0x13]	54133	1			T79	1		T85	28		T412	42
valid_sources[0x14]	54996	1			T79	8		T81	1		T85	19
valid_sources[0x15]	54439	1			T80	12		T81	1		T85	10
valid_sources[0x16]	54308	1			T79	4		T81	2		T85	23
valid_sources[0x17]	54068	1			T80	9		T81	1		T412	38
valid_sources[0x18]	54611	1			T80	4		T85	1		T412	35
valid_sources[0x19]	54287	1			T80	1		T81	1		T85	19
valid_sources[0x1a]	52436	1			T80	3		T85	25		T412	44
valid_sources[0x1b]	54473	1			T79	1		T80	5		T81	3
valid_sources[0x1c]	53871	1			T81	2		T85	37		T412	49
valid_sources[0x1d]	53759	1			T79	1		T81	1		T412	57
valid_sources[0x1e]	54728	1			T79	4		T81	1		T85	21
valid_sources[0x1f]	53858	1			T79	2		T81	1		T85	13
valid_sources[0x20]	54576	1			T80	13		T85	74		T412	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50885

1

T79

1

T80

3

T81

3

values[0x0]

all_enables

biggest_size

381656

1

T79

11

T80

11

T81

2

values[0x1]

all_enables

biggest_size

50393

1

T79

2

T80

1

T81

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2805853	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

443549

1

T79

12

T80

22

T81

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1102210	1			T79	63		T80	73		T81	24
values[0x0]	1048239	1			T79	50		T80	61		T81	4
values[0x1]	1098953	1			T79	44		T80	57		T81	29

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2172653	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1076749

1

T79

38

T80

60

T81

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50235	1			T79	4		T80	5		T81	1
valid_sources[0x01]	50784	1			T80	4		T81	2		T85	8
valid_sources[0x02]	50623	1			T80	4		T85	19		T412	47
valid_sources[0x03]	50672	1			T79	1		T80	4		T81	2
valid_sources[0x04]	50750	1			T80	7		T81	1		T85	10
valid_sources[0x05]	51065	1			T79	3		T85	5		T412	53
valid_sources[0x06]	51304	1			T79	2		T80	4		T81	1
valid_sources[0x07]	50185	1			T79	3		T80	8		T85	19
valid_sources[0x08]	50779	1			T79	1		T80	1		T81	1
valid_sources[0x09]	50629	1			T79	3		T80	1		T81	4
valid_sources[0x0a]	50799	1			T79	1		T80	2		T81	2
valid_sources[0x0b]	51934	1			T79	5		T80	9		T81	4
valid_sources[0x0c]	49497	1			T80	10		T81	1		T85	15
valid_sources[0x0d]	51386	1			T79	13		T80	5		T81	1
valid_sources[0x0e]	50817	1			T79	7		T80	4		T81	4
valid_sources[0x0f]	51576	1			T79	5		T80	4		T85	11
valid_sources[0x10]	50897	1			T79	2		T80	5		T85	12
valid_sources[0x11]	51161	1			T80	2		T81	1		T85	13
valid_sources[0x12]	50504	1			T79	5		T80	1		T85	4
valid_sources[0x13]	50563	1			T81	2		T85	17		T209	1
valid_sources[0x14]	51618	1			T79	2		T80	4		T85	3
valid_sources[0x15]	51406	1			T80	2		T85	6		T412	40
valid_sources[0x16]	51482	1			T80	1		T81	1		T85	15
valid_sources[0x17]	51010	1			T80	3		T85	4		T412	40
valid_sources[0x18]	50656	1			T79	9		T85	29		T412	58
valid_sources[0x19]	51050	1			T79	4		T85	7		T412	51
valid_sources[0x1a]	50757	1			T79	1		T85	16		T209	1
valid_sources[0x1b]	50521	1			T79	4		T80	2		T85	19
valid_sources[0x1c]	50774	1			T79	2		T81	1		T85	5
valid_sources[0x1d]	51679	1			T79	3		T80	8		T85	3
valid_sources[0x1e]	50636	1			T79	3		T80	2		T81	1
valid_sources[0x1f]	50623	1			T80	3		T85	8		T412	43
valid_sources[0x20]	49942	1			T79	12		T80	5		T81	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46751

1

T79

2

T81

1

T85

10

values[0x0]

all_enables

biggest_size

350363

1

T79

7

T80

19

T81

3

values[0x1]

all_enables

biggest_size

46435

1

T79

3

T80

3

T81

5