Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529667867	61112279	0	0
DepthKnown_A	529667867	529559704	0	0
RvalidKnown_A	529667867	529559704	0	0
WreadyKnown_A	529667867	529559704	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	61112279	0	0
T1	150373	10959	0	0
T2	153581	17008	0	0
T3	232542	23960	0	0
T4	221207	28845	0	0
T5	243698	32929	0	0
T15	189872	21306	0	0
T34	114872	10367	0	0
T48	134641	146968	0	0
T54	117291	18353	0	0
T90	244531	25509	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529667867	47147529	0	0
DepthKnown_A	529667867	529559704	0	0
RvalidKnown_A	529667867	529559704	0	0
WreadyKnown_A	529667867	529559704	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	47147529	0	0
T1	150373	8798	0	0
T2	153581	14526	0	0
T3	232542	20034	0	0
T4	221207	19317	0	0
T5	243698	28662	0	0
T15	189872	17381	0	0
T34	114872	7042	0	0
T48	134641	128032	0	0
T54	117291	12814	0	0
T90	244531	21602	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529667867	43824232	0	0
DepthKnown_A	529667867	529559704	0	0
RvalidKnown_A	529667867	529559704	0	0
WreadyKnown_A	529667867	529559704	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	43824232	0	0
T1	150373	7463	0	0
T2	153581	22776	0	0
T3	232542	22122	0	0
T4	221207	13739	0	0
T5	243698	14348	0	0
T15	189872	17557	0	0
T34	114872	5854	0	0
T48	134641	185674	0	0
T54	117291	8132	0	0
T90	244531	23216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529667867	36961077	0	0
DepthKnown_A	529667867	529559704	0	0
RvalidKnown_A	529667867	529559704	0	0
WreadyKnown_A	529667867	529559704	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	36961077	0	0
T1	150373	7267	0	0
T2	153581	22656	0	0
T3	232542	21917	0	0
T4	221207	13362	0	0
T5	243698	14092	0	0
T15	189872	17351	0	0
T34	114872	5625	0	0
T48	134641	119858	0	0
T54	117291	7941	0	0
T90	244531	23010	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529667867	529559704	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608998397	83375	0	0
DepthKnown_A	608998397	608874641	0	0
RvalidKnown_A	608998397	608874641	0	0
WreadyKnown_A	608998397	608874641	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	83375	0	0
T1	150373	13	0	0
T2	153581	118	0	0
T3	232542	53	0	0
T4	221207	151	0	0
T5	243698	30	0	0
T15	189872	53	0	0
T34	114872	26	0	0
T48	134641	34	0	0
T54	117291	17	0	0
T90	244531	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608998397	85074	0	0
DepthKnown_A	608998397	608874641	0	0
RvalidKnown_A	608998397	608874641	0	0
WreadyKnown_A	608998397	608874641	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	85074	0	0
T1	150373	13	0	0
T2	153581	118	0	0
T3	232542	53	0	0
T4	221207	151	0	0
T5	243698	30	0	0
T15	189872	53	0	0
T34	114872	26	0	0
T48	134641	34	0	0
T54	117291	17	0	0
T90	244531	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608998397	52206	0	0
DepthKnown_A	608998397	608874641	0	0
RvalidKnown_A	608998397	608874641	0	0
WreadyKnown_A	608998397	608874641	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	52206	0	0
T1	150373	12	0	0
T2	153581	16	0	0
T3	232542	52	0	0
T4	221207	95	0	0
T5	243698	23	0	0
T15	189872	52	0	0
T34	114872	24	0	0
T48	134641	5	0	0
T54	117291	12	0	0
T90	244531	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608998397	52206	0	0
DepthKnown_A	608998397	608874641	0	0
RvalidKnown_A	608998397	608874641	0	0
WreadyKnown_A	608998397	608874641	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	52206	0	0
T1	150373	12	0	0
T2	153581	16	0	0
T3	232542	52	0	0
T4	221207	95	0	0
T5	243698	23	0	0
T15	189872	52	0	0
T34	114872	24	0	0
T48	134641	5	0	0
T54	117291	12	0	0
T90	244531	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608998397	31169	0	0
DepthKnown_A	608998397	608874641	0	0
RvalidKnown_A	608998397	608874641	0	0
WreadyKnown_A	608998397	608874641	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	31169	0	0
T1	150373	1	0	0
T2	153581	102	0	0
T3	232542	1	0	0
T4	221207	56	0	0
T5	243698	7	0	0
T15	189872	1	0	0
T34	114872	2	0	0
T48	134641	29	0	0
T54	117291	5	0	0
T90	244531	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608998397	32868	0	0
DepthKnown_A	608998397	608874641	0	0
RvalidKnown_A	608998397	608874641	0	0
WreadyKnown_A	608998397	608874641	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	32868	0	0
T1	150373	1	0	0
T2	153581	102	0	0
T3	232542	1	0	0
T4	221207	56	0	0
T5	243698	7	0	0
T15	189872	1	0	0
T34	114872	2	0	0
T48	134641	29	0	0
T54	117291	5	0	0
T90	244531	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608998397	608874641	0	0
T1	150373	150322	0	0
T2	153581	153523	0	0
T3	232542	232487	0	0
T4	221207	221094	0	0
T5	243698	243643	0	0
T15	189872	189817	0	0
T34	114872	114756	0	0
T48	134641	134635	0	0
T54	117291	117240	0	0
T90	244531	244469	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T34	1	1	0	0
T48	1	1	0	0
T54	1	1	0	0
T90	1	1	0	0