Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T48,T90	Yes	T3,T48,T90	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T48,T90	Yes	T3,T48,T90	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T72,*T82	Yes	T49,T72,T82	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T60,T83,T84	Yes	T60,T83,T84	INPUT
tl_i.a_valid	Yes	Yes	T3,T54,T48	Yes	T3,T54,T48	INPUT
tl_o.a_ready	Yes	Yes	T3,T54,T48	Yes	T3,T54,T48	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T48,T90	Yes	T3,T48,T90	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T48,T90	Yes	T3,T54,T48	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T48,T90	Yes	T3,T54,T48	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T49,*T711,*T229	Yes	T49,T711,T229	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T48,*T90	Yes	T3,T48,T90	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T54,T48	Yes	T3,T54,T48	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	OUTPUT
cio_rx_i	Yes	Yes	T3,T4,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T3,T48,T90	Yes	T3,T48,T90	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T90,T89	Yes	T3,T90,T89	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T90,T89	Yes	T3,T90,T89	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T90,T89	Yes	T3,T90,T89	OUTPUT
intr_tx_done_o	Yes	Yes	T3,T90,T89	Yes	T3,T90,T89	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T90,T89	Yes	T3,T90,T89	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T48,T49	Yes	T3,T48,T49	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T48,T49	Yes	T3,T48,T49	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T72,*T82	Yes	T49,T72,T82	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T60,T83,T84	Yes	T60,T83,T84	INPUT
tl_i.a_valid	Yes	Yes	T3,T54,T48	Yes	T3,T54,T48	INPUT
tl_o.a_ready	Yes	Yes	T3,T54,T48	Yes	T3,T54,T48	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T48,T45	Yes	T3,T48,T45	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T48,T49	Yes	T3,T54,T48	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T48,T49	Yes	T3,T54,T48	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T49,*T711,*T229	Yes	T49,T711,T229	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T48,*T49	Yes	T3,T48,T49	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T54,T48	Yes	T3,T54,T48	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	OUTPUT
cio_rx_i	Yes	Yes	T3,T4,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T3,T48,T49	Yes	T3,T48,T49	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T282,T213	Yes	T3,T282,T213	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T282,T213	Yes	T3,T282,T213	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T282,T213	Yes	T3,T282,T213	OUTPUT
intr_tx_done_o	Yes	Yes	T3,T282,T213	Yes	T3,T282,T213	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T282,T213	Yes	T3,T282,T213	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T282,T44,T97	Yes	T282,T44,T97	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T282,T44,T97	Yes	T282,T44,T97	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T72,*T82	Yes	T49,T72,T82	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T60,T83,T84	Yes	T60,T83,T84	INPUT
tl_i.a_valid	Yes	Yes	T54,T282,T44	Yes	T54,T282,T44	INPUT
tl_o.a_ready	Yes	Yes	T54,T282,T44	Yes	T54,T282,T44	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T137	Yes	T80,T81,T137	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T282,T44,T97	Yes	T282,T44,T97	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T282,T44,T97	Yes	T54,T282,T44	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T282,T44,T97	Yes	T54,T282,T44	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T80,*T81,*T85	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T282,*T44,*T97	Yes	T282,T44,T97	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T54,T282,T44	Yes	T54,T282,T44	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	OUTPUT
cio_rx_i	Yes	Yes	T97,T312,T313	Yes	T9,T14,T97	INPUT
cio_tx_o	Yes	Yes	T97,T312,T313	Yes	T97,T312,T313	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T282,T97,T312	Yes	T282,T97,T312	OUTPUT
intr_tx_empty_o	Yes	Yes	T282,T97,T312	Yes	T282,T97,T312	OUTPUT
intr_rx_watermark_o	Yes	Yes	T282,T97,T312	Yes	T282,T97,T312	OUTPUT
intr_tx_done_o	Yes	Yes	T282,T97,T312	Yes	T282,T97,T312	OUTPUT
intr_rx_overflow_o	Yes	Yes	T282,T97,T312	Yes	T282,T97,T312	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T90,T89,T282	Yes	T90,T89,T282	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T90,T89,T282	Yes	T90,T89,T282	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T72,*T82	Yes	T49,T72,T82	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T60,T83,T84	Yes	T60,T83,T84	INPUT
tl_i.a_valid	Yes	Yes	T54,T90,T89	Yes	T54,T90,T89	INPUT
tl_o.a_ready	Yes	Yes	T54,T90,T89	Yes	T54,T90,T89	OUTPUT
tl_o.d_error	Yes	Yes	T79,T81,T85	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T90,T89,T282	Yes	T90,T89,T282	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T90,T89,T282	Yes	T54,T90,T89	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T90,T89,T282	Yes	T54,T90,T89	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T81,T85	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T81,*T85	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T81,T85	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T90,*T89,*T282	Yes	T90,T89,T282	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T54,T90,T89	Yes	T54,T90,T89	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	OUTPUT
cio_rx_i	Yes	Yes	T90,T89,T307	Yes	T90,T89,T307	INPUT
cio_tx_o	Yes	Yes	T90,T89,T307	Yes	T90,T89,T307	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T90,T89,T282	Yes	T90,T89,T282	OUTPUT
intr_tx_empty_o	Yes	Yes	T90,T89,T282	Yes	T90,T89,T282	OUTPUT
intr_rx_watermark_o	Yes	Yes	T90,T89,T282	Yes	T90,T89,T282	OUTPUT
intr_tx_done_o	Yes	Yes	T90,T89,T282	Yes	T90,T89,T282	OUTPUT
intr_rx_overflow_o	Yes	Yes	T90,T89,T282	Yes	T90,T89,T282	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T15,T282,T17	Yes	T15,T282,T17	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T15,T282,T17	Yes	T15,T282,T17	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T49,*T72,*T82	Yes	T49,T72,T82	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T60,T83,T84	Yes	T60,T83,T84	INPUT
tl_i.a_valid	Yes	Yes	T54,T15,T282	Yes	T54,T15,T282	INPUT
tl_o.a_ready	Yes	Yes	T54,T15,T282	Yes	T54,T15,T282	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T15,T282,T17	Yes	T15,T282,T17	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T15,T282,T17	Yes	T54,T15,T282	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T15,T282,T17	Yes	T54,T15,T282	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T80,*T81,*T85	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T80,T81,T85	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T15,*T282,*T17	Yes	T15,T282,T17	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T54,T15,T282	Yes	T54,T15,T282	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T1,T86,T163	Yes	T1,T86,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T54,T86	Yes	T1,T54,T86	OUTPUT
cio_rx_i	Yes	Yes	T15,T17,T294	Yes	T15,T17,T294	INPUT
cio_tx_o	Yes	Yes	T15,T17,T294	Yes	T15,T17,T294	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T15,T282,T17	Yes	T15,T282,T17	OUTPUT
intr_tx_empty_o	Yes	Yes	T15,T282,T17	Yes	T15,T282,T17	OUTPUT
intr_rx_watermark_o	Yes	Yes	T15,T282,T17	Yes	T15,T282,T17	OUTPUT
intr_tx_done_o	Yes	Yes	T15,T282,T17	Yes	T15,T282,T17	OUTPUT
intr_rx_overflow_o	Yes	Yes	T15,T282,T17	Yes	T15,T282,T17	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_break_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_timeout_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T282,T295,T308	Yes	T282,T295,T308	OUTPUT

*Tests covering at least one bit in the range