Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T80,T81,T209	Yes	T80,T81,T209	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T49,T68,T215	Yes	T49,T68,T215	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T49,T68,T215	Yes	T49,T68,T215	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T60,T83,T84	Yes	T60,T83,T84	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T60,T83,T201	Yes	T60,T83,T201	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T60,T83,T201	Yes	T60,T83,T201	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T4,T49,T67	Yes	T4,T49,T67	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T49,T52,T72	Yes	T49,T52,T72	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T34,T49	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T49,T52,T72	Yes	T49,T52,T72	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T49,T52,T72	Yes	T49,T52,T72	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T34,T49	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T49,T52,T72	Yes	T49,T52,T72	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T49,T52,T74	Yes	T49,T52,T74	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T49,T52,T72	Yes	T49,T52,T72	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T49,*T52,*T72	Yes	T49,T52,T72	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T49,T52,T72	Yes	T49,T52,T72	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T60,T79,T80	Yes	T60,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T60,T79,T81	Yes	T60,T79,T80	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T81,T85	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T60,*T79,*T80	Yes	T60,T79,T80	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T34,T49	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T49,T72,T82	Yes	T49,T72,T82	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T49,T72,T82	Yes	T49,T72,T82	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T49,T72,T82	Yes	T49,T72,T82	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T49,T72,T82	Yes	T49,T72,T82	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T49,T72,T82	Yes	T49,T72,T82	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T49,*T72,*T82	Yes	T49,T72,T82	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T49,T72,T82	Yes	T49,T72,T82	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T34,T49	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T49,T72,T82	Yes	T49,T72,T82	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T72,T82	Yes	T49,T72,T82	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T4,T34,T49	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T49,*T72,*T82	Yes	T49,T72,T82	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T4,T34,T49	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T49,T72,T82	Yes	T49,T72,T82	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T48,T52,T7	Yes	T48,T52,T7	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T48,T7,T382	Yes	T48,T7,T382	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T54,T34	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T60,T55	Yes	T54,T60,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T8,T243	Yes	T54,T8,T243	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T54,T8,T243	Yes	T54,T8,T243	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T54,T60,T55	Yes	T54,T60,T55	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T54,T8,T243	Yes	T54,T8,T243	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T60,*T79,*T80	Yes	T60,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T54,T8,T243	Yes	T54,T8,T243	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T54,T8,T243	Yes	T54,T8,T243	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T79,T80,T81	Yes	T80,T81,T85	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T8,T243,T383	Yes	T8,T243,T383	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T79,T80	Yes	T54,T60,T55	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T8,T243,T60	Yes	T54,T8,T243	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T80,T81,T85	Yes	T79,T80,T81	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T60,T80,T81	Yes	T60,T80,T81	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T80,T81,T85	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T8,*T243,*T60	Yes	T8,T243,T60	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T54,T8,T243	Yes	T54,T8,T243	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T49,*T72,*T82	Yes	T49,T72,T82	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T60,T83,T84	Yes	T60,T83,T84	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T68,T194,T215	Yes	T68,T194,T215	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T49,*T72,*T82	Yes	T49,T72,T82	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T54,T12,T13	Yes	T54,T12,T13	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T54,T12,T13	Yes	T54,T12,T13	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T12,T13	Yes	T54,T12,T13	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T54,T12,T13	Yes	T54,T12,T13	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T54,T12,T13	Yes	T54,T12,T13	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T54,T12,T13	Yes	T54,T12,T13	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T85	Yes	T80,T81,T85	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T96,T195,T196	Yes	T96,T195,T196	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T54,T12,T13	Yes	T54,T12,T13	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T54,T12,T13	Yes	T54,T12,T13	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T81,T85	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T12,T13,T14	Yes	T54,T12,T13	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T12,T13,T14	Yes	T12,T13,T14	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T81,T85	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T79,*T81,*T85	Yes	T79,T80,T81	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T79,T81,T85	Yes	T79,T80,T81	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T12,*T13,*T14	Yes	T12,T13,T14	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T54,T12,T13	Yes	T54,T12,T13	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T54,T44,T36	Yes	T54,T44,T36	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T54,T44,T36	Yes	T54,T44,T36	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T44,T36	Yes	T54,T44,T36	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T54,T44,T36	Yes	T54,T44,T36	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T54,T44,T36	Yes	T54,T44,T36	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T54,T44,T36	Yes	T54,T44,T36	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T85	Yes	T80,T81,T85	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T54,T44,T36	Yes	T54,T44,T36	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T54,T44,T36	Yes	T54,T44,T36	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T80,T81,T85	Yes	T79,T80,T81	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T44,T36,T160	Yes	T44,T36,T160	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T36,T160	Yes	T54,T44,T36	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T44,T36,T160	Yes	T44,T36,T160	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T209	Yes	T80,T81,T85	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T44,*T36,*T160	Yes	T44,T36,T160	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T54,T44,T36	Yes	T54,T44,T36	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T54,T219,T88	Yes	T54,T219,T88	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T54,T219,T76	Yes	T54,T219,T76	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T219,T88	Yes	T54,T219,T88	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T54,T219,T88	Yes	T54,T219,T88	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T54,T76,T282	Yes	T54,T76,T282	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T54,T219,T88	Yes	T54,T219,T88	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T54,T219,T88	Yes	T54,T219,T88	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T54,T219,T88	Yes	T54,T219,T88	INPUT
tl_usbdev_i.d_error	Yes	Yes	T81,T209,T137	Yes	T79,T81,T137	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T219,T282,T18	Yes	T219,T88,T282	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T219,T88,T76	Yes	T219,T76,T282	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T54,T219,T88	Yes	T219,T282,T18	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T209	Yes	T79,T80,T81	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T54,*T219,*T76	Yes	T219,T282,T18	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T54,T219,T88	Yes	T54,T219,T88	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T34,T64	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T4,T48,T34	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T79,T81,T85	Yes	T79,T81,T85	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T79,T81,T85	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T34,T64	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T54,T48	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T54,T48,T703	Yes	T54,T48,T703	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T48,T703	Yes	T54,T48,T703	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T54,T48,T703	Yes	T54,T48,T703	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T54,T48,T703	Yes	T54,T48,T703	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T54,T48,T703	Yes	T54,T48,T703	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T703,T238,T124	Yes	T703,T238,T124	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T54,T48,T703	Yes	T54,T48,T703	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T54,T48,T703	Yes	T54,T48,T703	INPUT
tl_hmac_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T48,T703,T45	Yes	T48,T703,T45	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T703,T45	Yes	T48,T703,T45	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T54,T48,T703	Yes	T48,T703,T45	INPUT
tl_hmac_i.d_sink	Yes	Yes	T79,T81,T85	Yes	T79,T80,T81	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T209	Yes	T79,T80,T81	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T80,T81,T85	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T54,*T48,*T703	Yes	T48,T703,T45	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T54,T48,T703	Yes	T54,T48,T703	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T54,T34	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T54,T159,T106	Yes	T54,T159,T106	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T159,T106	Yes	T54,T159,T106	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T54,T159,T106	Yes	T54,T159,T106	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T54,T159,T106	Yes	T54,T159,T106	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T54,T159,T106	Yes	T54,T159,T106	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T53,*T79,*T80	Yes	T53,T79,T80	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T408,T359,T409	Yes	T408,T359,T409	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T54,T159,T106	Yes	T54,T159,T106	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T54,T159,T106	Yes	T54,T159,T106	INPUT
tl_kmac_i.d_error	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T159,T106,T176	Yes	T159,T106,T176	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T159,T106,T176	Yes	T159,T106,T176	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T54,T159,T106	Yes	T176,T408,T134	INPUT
tl_kmac_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T53,*T81,*T85	Yes	T53,T79,T80	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T54,*T159,*T106	Yes	T176,T408,T134	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T54,T159,T106	Yes	T54,T159,T106	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T54,T34	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T54,T258,T259	Yes	T54,T258,T259	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T258,T259	Yes	T54,T258,T259	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T54,T258,T259	Yes	T54,T258,T259	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T54,T258,T259	Yes	T54,T258,T259	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T54,T258,T259	Yes	T54,T258,T259	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T60,*T84,*T53	Yes	T60,T84,T53	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T54,T258,T259	Yes	T54,T258,T259	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T54,T258,T259	Yes	T54,T258,T259	INPUT
tl_aes_i.d_error	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T258,T259,T132	Yes	T258,T259,T132	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T258,T259,T132	Yes	T54,T258,T259	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T258,T259,T132	Yes	T54,T258,T259	INPUT
tl_aes_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T80,T81,T85	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T60,*T84,*T53	Yes	T60,T84,T53	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T258,*T259,*T132	Yes	T258,T259,T132	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T54,T258,T259	Yes	T54,T258,T259	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T79,T81,T85	Yes	T79,T81,T85	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T131,T135,T136	Yes	T131,T135,T136	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T48,T34	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T48,T34	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T209	Yes	T79,T80,T81	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T131,*T135,*T136	Yes	T48,T131,T135	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T54,T131,T258	Yes	T54,T131,T258	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T60,*T84,*T53	Yes	T60,T84,T53	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T79,T81,T85	Yes	T79,T81,T85	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T131,T258,T136	Yes	T131,T258,T136	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T34,T131	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T34,T64	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T60,*T84,*T53	Yes	T60,T84,T53	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T131,*T258,*T136	Yes	T131,T258,T136	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T54,T131,T258	Yes	T54,T131,T258	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T54,T131,T258	Yes	T54,T131,T258	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T131,T258,T136	Yes	T131,T258,T136	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T34,T131	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T34,T131	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T80,T81,T85	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T209	Yes	T79,T80,T81	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T131,*T258,*T136	Yes	T131,T258,T136	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T54,T34	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T54,T131,T136	Yes	T54,T131,T136	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T131,T136	Yes	T54,T131,T136	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T54,T131,T136	Yes	T54,T131,T136	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T54,T131,T136	Yes	T54,T131,T136	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T54,T131,T136	Yes	T54,T131,T136	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T54,T131,T136	Yes	T54,T131,T136	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T54,T131,T136	Yes	T54,T131,T136	INPUT
tl_edn1_i.d_error	Yes	Yes	T80,T81,T137	Yes	T80,T81,T137	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T131,T136,T259	Yes	T131,T136,T259	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T131,T259,T132	Yes	T54,T131,T136	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T131,T259,T132	Yes	T54,T131,T136	INPUT
tl_edn1_i.d_sink	Yes	Yes	T80,T81,T85	Yes	T80,T81,T85	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T137	Yes	T79,T80,T81	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T80,T81,T85	Yes	T79,T80,T81	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T131,*T136,*T259	Yes	T131,T136,T259	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T54,T131,T136	Yes	T54,T131,T136	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T3,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T54	Yes	T3,T4,T54	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T54	Yes	T3,T4,T54	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T54	Yes	T3,T4,T54	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T4,T54	Yes	T3,T4,T54	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T4,T54	Yes	T3,T4,T54	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T4,T54	Yes	T3,T4,T54	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T4,T54	Yes	T3,T4,T54	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T79,T80,T81	Yes	T80,T81,T85	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T15	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T54	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T4,T15	Yes	T3,T4,T54	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T80,T81,T85	Yes	T79,T80,T81	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T85	Yes	T79,T80,T81	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T80,T81,T85	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T15	Yes	T3,T4,T15	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T4,T54	Yes	T3,T4,T54	INPUT
tl_otbn_o.d_ready	Yes	Yes	T2,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T2,T54,T48	Yes	T2,T54,T48	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T54,T48	Yes	T2,T54,T48	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T2,T54,T48	Yes	T2,T54,T48	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T2,T54,T48	Yes	T2,T54,T48	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T2,T54,T48	Yes	T2,T54,T48	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T83,*T200,*T201	Yes	T83,T200,T201	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T2,T54,T48	Yes	T2,T54,T48	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T2,T54,T48	Yes	T2,T54,T48	INPUT
tl_otbn_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T2,T48,T131	Yes	T2,T48,T131	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T48,T131	Yes	T2,T48,T131	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T2,T54,T48	Yes	T2,T48,T131	INPUT
tl_otbn_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T83,*T200,*T201	Yes	T83,T200,T201	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T2,*T54,*T48	Yes	T2,T48,T131	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T2,T54,T48	Yes	T2,T54,T48	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T54,T48	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T54,T48,T159	Yes	T54,T48,T159	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T48,T159	Yes	T54,T48,T159	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T54,T48,T159	Yes	T54,T48,T159	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T54,T48,T159	Yes	T54,T48,T159	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T54,T48,T159	Yes	T54,T48,T159	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T79,T81,T85	Yes	T79,T81,T85	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T54,T48,T159	Yes	T54,T48,T159	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T54,T48,T159	Yes	T54,T48,T159	INPUT
tl_keymgr_i.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T159,T106,T176	Yes	T159,T106,T176	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T159,T106	Yes	T54,T48,T159	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T48,T159,T106	Yes	T54,T48,T159	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T79,T81,T85	Yes	T79,T80,T81	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T209	Yes	T79,T80,T81	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T81,T85	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T48,*T159,*T106	Yes	T48,T159,T106	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T54,T48,T159	Yes	T54,T48,T159	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T49,*T60,*T229	Yes	T49,T60,T229	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T60,T79,T80	Yes	T60,T79,T80	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T48	Yes	T2,T4,T48	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T4,T48	Yes	T2,T4,T48	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T60,*T79,*T81	Yes	T49,T60,T229	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T54,T48	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T48,T49	Yes	T54,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T48,T49	Yes	T54,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T54,T48,T49	Yes	T54,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T54,T48,T49	Yes	T54,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T54,T48,T49	Yes	T54,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T400,*T401,*T402	Yes	T400,T401,T402	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T54,T48,T49	Yes	T54,T48,T49	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T54,T48,T49	Yes	T54,T48,T49	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T79,T80,T81	Yes	T80,T81,T85	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T183,T184,T185	Yes	T183,T184,T185	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T122,T45,T46	Yes	T54,T48,T49	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T122,T45,T46	Yes	T54,T48,T49	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T81,*T85,*T209	Yes	T400,T401,T402	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T79,T81,T85	Yes	T79,T80,T81	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T122,*T177,*T125	Yes	T122,T217,T218	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T54,T48,T49	Yes	T54,T48,T49	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T4,T34,T49	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range