dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[21].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[22].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[23].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[24].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[25].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[26].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[27].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[28].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[29].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[30].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[31].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[32].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[33].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[34].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[35].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[36].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[37].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[38].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[39].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[40].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[41].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[42].u_mio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT5,T16,T111
01CoveredT5,T16,T111
10CoveredT31,T32,T33
11CoveredT31,T32,T37

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT5,T16,T111
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT5,T16,T111

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT5,T16,T111
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T16,T111

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT5,T16,T111

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T5,T16,T111
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT48,T49,T7
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT10,T31,T32
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT9,T10,T11

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT9,T10,T11
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT9,T10,T11

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT48,T49,T45

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T48,T49,T45
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T89,T9
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT10,T11,T31
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT10,T11,T31

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT10,T11,T31
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T31

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT10,T11,T31

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT48,T49,T45

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T10,T11,T31
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T48,T49,T45
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T89,T9
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT10,T31,T32

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT10,T31,T32
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T31,T32

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT10,T31,T32

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT48,T49,T45

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T10,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T48,T49,T45
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT3,T213,T214
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT9,T31,T32
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT9,T10,T11

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT9,T10,T11
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT9,T10,T11

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT3,T48,T49
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT1,T2,T3
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT1,T2,T3
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT49,T52,T72
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT11,T31,T32

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT11,T31,T32
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T31,T32

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT11,T31,T32

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T11,T31,T32
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT71,T50,T126
01CoveredT71,T50,T126
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT9,T31,T32
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT9,T10,T11

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT9,T10,T11
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T10,T11

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT9,T10,T11

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT22,T88,T203
01CoveredT22,T88,T203
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT22,T9,T24
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT22,T9,T24

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT22,T9,T24
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T9,T24

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT22,T9,T24

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T22,T9,T24
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T52,T71
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT11,T31,T32
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT9,T11,T31

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT9,T11,T31
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T11,T31

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT9,T11,T31

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T9,T11,T31
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT22,T16,T203
01CoveredT22,T16,T203
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT22,T16,T27
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT22,T16,T27

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT22,T16,T27
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T16,T27

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT22,T16,T27

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T22,T16,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT5,T16,T111
01CoveredT5,T16,T111
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT5,T16,T111
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT5,T16,T111

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT5,T16,T111
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T16,T111

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT5,T16,T111

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T5,T16,T111
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT5,T16,T111
01CoveredT5,T16,T111
10CoveredT31,T32,T37
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT5,T16,T111
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT5,T16,T111

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT5,T16,T111
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T16,T111

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT5,T16,T111

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T5,T16,T111
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT5,T16,T111
01CoveredT5,T16,T111
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT5,T16,T111
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT5,T16,T111

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT5,T16,T111
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T16,T111

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT5,T16,T111

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T5,T16,T111
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT49,T6,T52
01CoveredT49,T6,T52
10CoveredT31,T32,T37
11CoveredT31,T32,T37

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT16,T9,T27
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T9,T27

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT16,T9,T27
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T9,T27

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T9,T27

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T9,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT49,T6,T52
01CoveredT49,T6,T52
10CoveredT31,T32,T33
11CoveredT31,T33,T188

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT49,T6,T52
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT49,T6,T52

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT49,T6,T52
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49,T6,T52

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT49,T6,T52

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T49,T6,T52
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT49,T6,T52
01CoveredT49,T6,T52
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT16,T9,T27
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T9,T27

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT16,T9,T27
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T9,T27

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T9,T27

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T9,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT49,T6,T52
01CoveredT49,T6,T52
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT16,T27,T44
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T27,T44

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT16,T27,T44
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T27,T44

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T27,T44

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T27,T44
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT49,T6,T52
01CoveredT49,T6,T52
10CoveredT31,T32,T33
11CoveredT31,T33,T37

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT16,T9,T27
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T9,T27

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT16,T9,T27
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T9,T27

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T9,T27

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T9,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT52,T22,T16
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT22,T16,T27
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT22,T16,T27

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT22,T16,T27
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T16,T27

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT22,T16,T27

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T22,T16,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT22,T16,T9
01CoveredT22,T16,T9
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT22,T16,T27
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT22,T16,T27

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT22,T16,T27
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T16,T27

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT22,T16,T27

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T22,T16,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT31,T32,T33
11CoveredT1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT31,T32,T33
1CoveredT1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T75,T9
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10CoveredT16,T9,T27
11CoveredT31,T32,T33

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T9,T27

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT31,T32,T33
01CoveredT1,T2,T3
10CoveredT31,T32,T33

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT31,T32,T33

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT31,T32,T33
10CoveredT16,T9,T27
11CoveredT31,T32,T33

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT16,T9,T27

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T32,T33
11CoveredT16,T9,T27

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T32,T33

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T31,T32,T33


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T16,T9,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T31,T32,T33
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 1027 1027 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1027 1027 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T34 1 1 0 0
T48 1 1 0 0
T54 1 1 0 0
T90 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%