Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3716106	1			T70	1632		T71	281		T72	70
values[2]	754551	1			T70	506		T71	71		T72	56
values[3]	107256	1			T70	7		T71	1		T139	17
values[4]	56644	1			T139	2		T447	2		T436	61
values[5]	37597	1			T447	4		T436	41		T448	13
values[6]	27702	1			T447	5		T436	34		T448	4
values[7]	22248	1			T447	4		T436	34		T448	1
values[8]	18710	1			T447	5		T436	45		T448	4
values[9]	16481	1			T447	3		T436	46		T448	3
values[10]	15127	1			T447	4		T436	42		T448	6
values[11]	14182	1			T447	5		T436	43		T448	8
values[12]	13304	1			T447	1		T436	40		T448	16
values[13]	12495	1			T436	32		T448	10		T549	30
values[14]	12147	1			T436	39		T448	4		T549	20
values[15]	11418	1			T436	15		T448	2		T549	20
values[16]	11092	1			T436	19		T448	10		T549	8
values[17]	10703	1			T436	21		T448	16		T549	6
values[18]	10260	1			T436	42		T448	12		T549	9
values[19]	9892	1			T436	35		T448	3		T549	7
values[20]	9315	1			T436	24		T448	3		T549	9
values[21]	9310	1			T436	25		T448	11		T549	20
values[22]	8952	1			T436	57		T448	4		T549	11
values[23]	8509	1			T436	32		T448	7		T549	9
values[24]	8191	1			T436	33		T448	4		T549	8
values[25]	7785	1			T436	29		T448	6		T549	6
values[26]	7683	1			T436	31		T448	3		T549	9
values[27]	7048	1			T436	40		T448	2		T549	6
values[28]	6774	1			T436	42		T448	10		T549	4
values[29]	6564	1			T436	31		T448	2		T549	7
values[30]	6113	1			T436	18		T448	1		T549	10
values[31]	5681	1			T436	15		T549	10		T822	5
values[32]	5319	1			T436	7		T549	6		T822	5
values[33]	4898	1			T436	9		T549	6		T822	5
values[34]	4432	1			T436	8		T549	6		T822	5
values[35]	4132	1			T436	10		T549	6		T822	5
values[36]	3935	1			T436	10		T549	5		T822	5
values[37]	3726	1			T436	7		T549	9		T822	5
values[38]	3594	1			T436	5		T549	11		T822	5
values[39]	3402	1			T436	9		T549	8		T822	5
values[40]	3333	1			T436	4		T549	8		T822	5
values[41]	3122	1			T436	9		T549	4		T822	5
values[42]	3145	1			T436	8		T549	4		T822	5
values[43]	3050	1			T436	11		T549	6		T822	5
values[44]	2940	1			T436	3		T549	7		T822	5
values[45]	2916	1			T436	10		T549	12		T822	5
values[46]	2858	1			T436	8		T549	9		T822	5
values[47]	2947	1			T436	3		T549	5		T822	5
values[48]	2831	1			T436	8		T549	7		T822	5
values[49]	2791	1			T436	5		T549	9		T822	5
values[50]	2742	1			T436	2		T549	7		T822	5
values[51]	2729	1			T436	7		T549	11		T822	5
values[52]	2598	1			T436	1		T549	9		T822	5
values[53]	2537	1			T436	5		T549	5		T822	6
values[54]	2557	1			T436	3		T549	9		T822	5
values[55]	2492	1			T436	4		T549	11		T822	5
values[56]	2528	1			T436	2		T549	11		T822	5
values[57]	2373	1			T436	2		T549	8		T822	5
values[58]	2379	1			T436	1		T549	6		T822	5
values[59]	2338	1			T436	2		T549	7		T822	5
values[60]	2361	1			T436	3		T549	5		T822	5
values[61]	2630	1			T436	6		T549	9		T822	5
values[62]	4000	1			T436	2		T549	20		T822	5
values[63]	10494	1			T436	3		T549	99		T822	6
values[64]	216497	1			T549	339		T822	920		T459	514

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4738965	1			T70	1826		T71	606		T72	102
values[2]	802318	1			T70	461		T71	114		T72	23
values[3]	82213	1			T70	77		T71	1		T72	4
values[4]	14648	1			T139	10		T447	9		T436	1
values[5]	5513	1			T139	3		T447	1		T549	32
values[6]	3512	1			T139	2		T549	26		T822	1
values[7]	2649	1			T549	34		T459	1		T517	1
values[8]	2227	1			T549	51		T517	2		T912	2
values[9]	1938	1			T549	26		T517	1		T912	4
values[10]	1639	1			T549	25		T517	3		T912	5
values[11]	1537	1			T549	18		T517	4		T912	2
values[12]	1394	1			T549	18		T517	2		T912	4
values[13]	1269	1			T549	30		T517	3		T912	6
values[14]	1116	1			T549	23		T517	1		T912	6
values[15]	1083	1			T549	21		T517	1		T912	7
values[16]	994	1			T549	19		T517	1		T912	8
values[17]	906	1			T549	4		T517	1		T912	10
values[18]	859	1			T549	1		T517	1		T912	20
values[19]	927	1			T549	4		T517	2		T912	14
values[20]	921	1			T549	4		T517	5		T912	15
values[21]	862	1			T549	4		T517	3		T912	5
values[22]	770	1			T549	3		T517	2		T912	5
values[23]	763	1			T549	4		T517	1		T912	5
values[24]	692	1			T549	4		T517	1		T912	1
values[25]	621	1			T549	4		T517	1		T912	3
values[26]	635	1			T549	3		T517	1		T912	2
values[27]	569	1			T549	1		T517	2		T912	1
values[28]	611	1			T549	1		T517	6		T912	5
values[29]	596	1			T549	1		T517	2		T912	13
values[30]	547	1			T549	1		T517	4		T912	3
values[31]	587	1			T549	1		T517	2		T912	1
values[32]	531	1			T549	2		T517	2		T912	3
values[33]	546	1			T549	3		T517	2		T912	9
values[34]	504	1			T549	1		T517	2		T912	10
values[35]	531	1			T549	1		T517	2		T912	7
values[36]	491	1			T549	3		T517	1		T912	10
values[37]	491	1			T549	4		T517	2		T912	8
values[38]	465	1			T549	1		T517	1		T912	10
values[39]	418	1			T549	1		T517	1		T912	11
values[40]	366	1			T549	2		T517	2		T912	9
values[41]	359	1			T549	1		T517	1		T912	2
values[42]	440	1			T549	2		T517	2		T912	4
values[43]	395	1			T549	2		T517	1		T912	2
values[44]	392	1			T549	2		T517	1		T912	3
values[45]	403	1			T549	1		T517	1		T912	1
values[46]	445	1			T549	1		T517	2		T661	1
values[47]	408	1			T549	1		T517	2		T661	1
values[48]	402	1			T549	3		T517	2		T661	1
values[49]	433	1			T549	4		T517	1		T661	1
values[50]	415	1			T549	5		T517	2		T661	1
values[51]	411	1			T549	4		T517	2		T661	3
values[52]	383	1			T549	4		T517	1		T661	1
values[53]	372	1			T549	5		T517	2		T661	2
values[54]	350	1			T549	2		T517	1		T661	1
values[55]	359	1			T549	1		T517	1		T661	2
values[56]	353	1			T549	1		T517	1		T661	5
values[57]	384	1			T549	1		T517	1		T661	2
values[58]	375	1			T549	1		T517	1		T661	3
values[59]	358	1			T549	1		T517	1		T661	3
values[60]	352	1			T549	1		T517	2		T661	2
values[61]	431	1			T549	3		T517	2		T661	4
values[62]	709	1			T549	4		T517	4		T661	3
values[63]	2659	1			T549	25		T517	38		T661	3
values[64]	26827	1			T549	31		T517	134		T661	154

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	576897	1			T70	30		T71	103		T72	3
values[2]	2614604	1			T70	748		T71	144		T72	58
values[3]	1218467	1			T70	1346		T71	61		T72	47
values[4]	146616	1			T70	32		T71	17		T72	2
values[5]	74901	1			T71	5		T139	6		T447	37
values[6]	49251	1			T71	1		T447	32		T436	33
values[7]	35615	1			T447	27		T436	32		T549	172
values[8]	28267	1			T447	31		T436	36		T549	133
values[9]	23314	1			T447	14		T436	26		T549	56
values[10]	20406	1			T447	10		T436	48		T549	62
values[11]	18078	1			T447	5		T436	28		T549	62
values[12]	16609	1			T447	3		T436	40		T549	100
values[13]	15074	1			T447	6		T436	29		T549	83
values[14]	14284	1			T447	8		T436	39		T549	59
values[15]	13750	1			T447	1		T436	46		T549	50
values[16]	13371	1			T436	74		T549	22		T822	5
values[17]	12736	1			T436	66		T549	23		T822	5
values[18]	12377	1			T436	33		T549	34		T822	5
values[19]	12104	1			T436	33		T549	57		T822	5
values[20]	11455	1			T436	55		T549	45		T822	6
values[21]	10929	1			T436	44		T549	47		T822	5
values[22]	10405	1			T436	33		T549	27		T822	5
values[23]	10013	1			T436	34		T549	27		T822	5
values[24]	9380	1			T436	19		T549	22		T822	5
values[25]	8850	1			T436	29		T549	16		T822	5
values[26]	8375	1			T436	39		T549	13		T822	5
values[27]	8077	1			T436	30		T549	15		T822	5
values[28]	7929	1			T436	31		T549	11		T822	5
values[29]	7246	1			T436	16		T549	12		T822	5
values[30]	6517	1			T436	16		T549	12		T822	5
values[31]	6172	1			T436	12		T549	18		T822	5
values[32]	6137	1			T436	7		T549	23		T822	5
values[33]	5619	1			T436	5		T549	6		T822	5
values[34]	5161	1			T436	12		T549	7		T822	5
values[35]	4753	1			T436	10		T549	6		T822	5
values[36]	4496	1			T436	3		T549	6		T822	5
values[37]	4280	1			T549	5		T822	5		T519	23
values[38]	4039	1			T549	10		T822	5		T519	24
values[39]	3824	1			T549	6		T822	5		T519	21
values[40]	3674	1			T549	5		T822	5		T519	15
values[41]	3627	1			T549	16		T822	5		T519	15
values[42]	3541	1			T549	8		T822	5		T519	11
values[43]	3484	1			T549	12		T822	5		T519	9
values[44]	3432	1			T549	14		T822	5		T519	10
values[45]	3295	1			T549	11		T822	5		T519	9
values[46]	3296	1			T549	12		T822	5		T519	8
values[47]	3170	1			T549	8		T822	5		T519	6
values[48]	3278	1			T549	9		T822	5		T519	8
values[49]	3150	1			T549	5		T822	5		T519	11
values[50]	3076	1			T549	3		T822	6		T519	5
values[51]	3042	1			T549	9		T822	5		T519	2
values[52]	2905	1			T549	7		T822	5		T519	1
values[53]	2963	1			T549	13		T822	6		T519	3
values[54]	2902	1			T549	15		T822	5		T519	2
values[55]	2844	1			T549	13		T822	5		T519	3
values[56]	2794	1			T549	4		T822	6		T519	6
values[57]	2689	1			T549	4		T822	5		T519	1
values[58]	2582	1			T549	3		T822	5		T519	1
values[59]	2516	1			T549	10		T822	5		T519	2
values[60]	2541	1			T549	6		T822	5		T519	1
values[61]	2610	1			T549	4		T822	5		T519	4
values[62]	3429	1			T549	15		T822	5		T519	4
values[63]	8842	1			T549	43		T822	5		T519	2
values[64]	210178	1			T549	80		T822	866		T519	2