Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2266335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37150754

1

T1

110971

T2

10224

T3

8263

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27683711	1			T1	98587		T2	3723		T3	3948
values[0x0]	10258320	1			T1	12384		T2	6501		T3	4315
values[0x1]	1475058	1			T1	5		T2	624		T3	476

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	877449	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38539640

1

T1

110976

T2

10848

T3

8739

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18204599	1			T1	55488		T2	5425		T3	4370
valid_sources[0x01]	18204155	1			T1	55488		T2	5423		T3	4369
valid_sources[0x02]	48421	1			T132	1		T113	353		T375	91
valid_sources[0x03]	48066	1			T113	409		T375	76		T550	33
valid_sources[0x04]	48030	1			T133	2		T113	339		T375	81
valid_sources[0x05]	49131	1			T132	1		T113	371		T375	84
valid_sources[0x06]	47891	1			T113	441		T375	74		T550	22
valid_sources[0x07]	48058	1			T132	1		T133	1		T113	423
valid_sources[0x08]	48324	1			T133	4		T113	365		T375	99
valid_sources[0x09]	49029	1			T132	2		T133	2		T113	441
valid_sources[0x0a]	47994	1			T113	361		T375	73		T550	11
valid_sources[0x0b]	48439	1			T132	2		T113	329		T375	83
valid_sources[0x0c]	48599	1			T113	429		T375	81		T550	32
valid_sources[0x0d]	55922	1			T132	2		T113	335		T375	79
valid_sources[0x0e]	48937	1			T113	428		T375	99		T550	47
valid_sources[0x0f]	48526	1			T133	1		T113	433		T375	95
valid_sources[0x10]	47895	1			T133	1		T113	439		T375	103
valid_sources[0x11]	48401	1			T76	4		T133	2		T113	382
valid_sources[0x12]	48007	1			T76	4		T133	1		T113	381
valid_sources[0x13]	48380	1			T184	39		T113	491		T375	90
valid_sources[0x14]	48153	1			T132	1		T113	360		T375	62
valid_sources[0x15]	48752	1			T76	6		T132	1		T133	1
valid_sources[0x16]	48071	1			T113	368		T375	78		T550	10
valid_sources[0x17]	47859	1			T132	1		T133	1		T113	425
valid_sources[0x18]	48989	1			T133	3		T113	414		T375	76
valid_sources[0x19]	48091	1			T132	1		T133	1		T113	423
valid_sources[0x1a]	48599	1			T132	2		T113	388		T375	92
valid_sources[0x1b]	48891	1			T133	1		T113	319		T375	94
valid_sources[0x1c]	48880	1			T132	2		T113	379		T375	72
valid_sources[0x1d]	48894	1			T132	1		T133	2		T113	385
valid_sources[0x1e]	48567	1			T132	1		T113	448		T375	100
valid_sources[0x1f]	48540	1			T132	1		T113	434		T375	79
valid_sources[0x20]	48850	1			T113	370		T375	72		T550	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26668053

1

T1

98587

T2

3723

T3

3948

values[0x0]

all_enables

biggest_size

10201692

1

T1

12384

T2

6501

T3

4315

values[0x1]

all_enables

biggest_size

281009

1

T74

16

T75

18

T76

25

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2888380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

457884

1

T70

283

T71

2

T72

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1132582	1			T70	699		T71	8		T72	41
values[0x0]	1081739	1			T70	700		T72	41		T77	135
values[0x1]	1131943	1			T70	746		T71	7		T72	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2236909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1109355

1

T70

696

T71

9

T72

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51828	1			T70	42		T77	6		T138	32
valid_sources[0x01]	52463	1			T70	28		T77	8		T449	8
valid_sources[0x02]	52038	1			T70	31		T72	4		T77	6
valid_sources[0x03]	51637	1			T70	35		T77	10		T138	20
valid_sources[0x04]	52539	1			T70	29		T72	3		T77	5
valid_sources[0x05]	51294	1			T70	20		T71	2		T72	3
valid_sources[0x06]	52349	1			T70	23		T77	7		T138	39
valid_sources[0x07]	51793	1			T70	63		T72	1		T77	5
valid_sources[0x08]	52509	1			T70	26		T72	1		T77	3
valid_sources[0x09]	53806	1			T70	33		T71	1		T72	2
valid_sources[0x0a]	52687	1			T70	43		T77	6		T138	34
valid_sources[0x0b]	51578	1			T70	28		T72	5		T77	4
valid_sources[0x0c]	52419	1			T70	45		T72	7		T77	6
valid_sources[0x0d]	52573	1			T70	30		T72	2		T77	2
valid_sources[0x0e]	51980	1			T70	50		T77	9		T138	22
valid_sources[0x0f]	51965	1			T70	21		T71	1		T72	4
valid_sources[0x10]	51261	1			T70	20		T77	5		T138	70
valid_sources[0x11]	52083	1			T70	80		T77	4		T138	34
valid_sources[0x12]	53044	1			T70	17		T77	8		T138	61
valid_sources[0x13]	52559	1			T70	48		T72	3		T77	3
valid_sources[0x14]	52434	1			T70	52		T77	9		T138	25
valid_sources[0x15]	53299	1			T70	18		T72	1		T77	7
valid_sources[0x16]	51386	1			T70	34		T72	7		T77	4
valid_sources[0x17]	50363	1			T70	31		T77	4		T138	13
valid_sources[0x18]	52590	1			T70	22		T71	1		T77	12
valid_sources[0x19]	52982	1			T70	57		T77	6		T138	53
valid_sources[0x1a]	52022	1			T70	30		T77	4		T138	26
valid_sources[0x1b]	52514	1			T70	58		T71	1		T72	5
valid_sources[0x1c]	52650	1			T70	39		T77	10		T447	1
valid_sources[0x1d]	51768	1			T70	22		T77	5		T138	9
valid_sources[0x1e]	52557	1			T70	29		T71	1		T77	4
valid_sources[0x1f]	52747	1			T70	18		T77	6		T139	12
valid_sources[0x20]	52234	1			T70	25		T77	6		T138	54

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47782

1

T70

23

T72

1

T77

6

values[0x0]

all_enables

biggest_size

361834

1

T70

242

T72

18

T77

43

values[0x1]

all_enables

biggest_size

48268

1

T70

18

T71

2

T72

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3082868	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

503520

1

T70

343

T71

2

T72

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1225663	1			T70	793		T71	15		T72	49
values[0x0]	1133416	1			T70	741		T71	2		T72	32
values[0x1]	1227309	1			T70	830		T71	15		T72	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2367140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1219248

1

T70

783

T71

9

T72

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55597	1			T70	14		T71	2		T77	8
valid_sources[0x01]	55211	1			T70	60		T71	1		T449	7
valid_sources[0x02]	54852	1			T70	44		T71	2		T77	13
valid_sources[0x03]	56336	1			T70	69		T72	4		T138	8
valid_sources[0x04]	55489	1			T70	30		T138	6		T449	18
valid_sources[0x05]	56119	1			T70	31		T77	6		T138	31
valid_sources[0x06]	55926	1			T70	22		T71	1		T138	29
valid_sources[0x07]	55606	1			T70	32		T72	4		T77	29
valid_sources[0x08]	55716	1			T70	44		T71	1		T138	11
valid_sources[0x09]	55885	1			T70	51		T72	23		T138	7
valid_sources[0x0a]	56273	1			T70	29		T138	50		T449	11
valid_sources[0x0b]	55446	1			T70	44		T71	2		T138	27
valid_sources[0x0c]	55976	1			T70	56		T71	1		T72	4
valid_sources[0x0d]	56818	1			T70	44		T72	1		T77	7
valid_sources[0x0e]	55823	1			T70	42		T71	1		T77	9
valid_sources[0x0f]	55576	1			T70	76		T71	1		T77	8
valid_sources[0x10]	56036	1			T70	46		T77	3		T138	60
valid_sources[0x11]	56925	1			T70	37		T71	1		T77	13
valid_sources[0x12]	56629	1			T70	25		T71	1		T77	2
valid_sources[0x13]	55374	1			T70	19		T71	1		T77	29
valid_sources[0x14]	57065	1			T70	31		T71	1		T77	6
valid_sources[0x15]	56941	1			T70	24		T72	4		T138	44
valid_sources[0x16]	55486	1			T70	5		T138	38		T139	7
valid_sources[0x17]	56073	1			T70	42		T77	17		T138	13
valid_sources[0x18]	56525	1			T70	11		T138	55		T139	6
valid_sources[0x19]	55691	1			T70	20		T77	21		T138	46
valid_sources[0x1a]	57351	1			T70	30		T77	45		T138	26
valid_sources[0x1b]	55622	1			T70	16		T71	1		T138	20
valid_sources[0x1c]	55779	1			T70	22		T72	11		T139	14
valid_sources[0x1d]	55228	1			T70	46		T71	1		T72	3
valid_sources[0x1e]	55835	1			T70	20		T72	5		T138	26
valid_sources[0x1f]	55037	1			T70	59		T72	8		T77	11
valid_sources[0x20]	55043	1			T70	35		T77	27		T138	54

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52423

1

T70

43

T72

3

T77

6

values[0x0]

all_enables

biggest_size

398399

1

T70

269

T71

1

T72

11

values[0x1]

all_enables

biggest_size

52698

1

T70

31

T71

1

T72

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2917828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

461591

1

T70

292

T71

2

T72

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1144539	1			T70	736		T71	10		T72	41
values[0x0]	1090196	1			T70	702		T71	1		T72	33
values[0x1]	1144684	1			T70	718		T71	4		T72	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2258987	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1120432

1

T70

685

T71

9

T72

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51439	1			T70	30		T77	3		T138	29
valid_sources[0x01]	52594	1			T70	25		T71	1		T72	1
valid_sources[0x02]	52135	1			T70	45		T72	3		T77	11
valid_sources[0x03]	52758	1			T70	41		T77	12		T138	17
valid_sources[0x04]	51763	1			T70	25		T77	17		T138	5
valid_sources[0x05]	52162	1			T70	35		T77	1		T138	23
valid_sources[0x06]	54308	1			T70	36		T72	2		T138	46
valid_sources[0x07]	52432	1			T70	30		T72	3		T77	10
valid_sources[0x08]	52692	1			T70	34		T77	1		T138	6
valid_sources[0x09]	52892	1			T70	38		T77	3		T138	19
valid_sources[0x0a]	53468	1			T70	46		T77	13		T138	33
valid_sources[0x0b]	54346	1			T70	46		T72	3		T138	17
valid_sources[0x0c]	52236	1			T70	32		T72	5		T138	24
valid_sources[0x0d]	53114	1			T70	53		T72	2		T77	7
valid_sources[0x0e]	52963	1			T70	31		T72	4		T77	5
valid_sources[0x0f]	52460	1			T70	24		T71	1		T72	3
valid_sources[0x10]	51902	1			T70	31		T72	2		T77	2
valid_sources[0x11]	52956	1			T70	32		T71	1		T138	44
valid_sources[0x12]	53105	1			T70	27		T77	21		T138	58
valid_sources[0x13]	53716	1			T70	39		T71	1		T72	2
valid_sources[0x14]	52460	1			T70	31		T72	2		T77	9
valid_sources[0x15]	51766	1			T70	20		T77	4		T138	52
valid_sources[0x16]	52420	1			T70	28		T72	2		T77	13
valid_sources[0x17]	51436	1			T70	28		T72	3		T77	5
valid_sources[0x18]	53201	1			T70	27		T138	59		T139	7
valid_sources[0x19]	53264	1			T70	41		T77	28		T138	35
valid_sources[0x1a]	52933	1			T70	33		T72	3		T77	4
valid_sources[0x1b]	53133	1			T70	30		T71	2		T72	4
valid_sources[0x1c]	52880	1			T70	27		T77	8		T139	1
valid_sources[0x1d]	51897	1			T70	43		T72	1		T138	11
valid_sources[0x1e]	52466	1			T70	34		T72	2		T77	8
valid_sources[0x1f]	52631	1			T70	33		T72	2		T77	3
valid_sources[0x20]	52569	1			T70	41		T71	1		T72	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48474

1

T70

39

T71

1

T72

1

values[0x0]

all_enables

biggest_size

364738

1

T70

229

T71

1

T72

6

values[0x1]

all_enables

biggest_size

48379

1

T70

24

T72

2

T77

6