Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516776511	60191372	0	0
DepthKnown_A	516776511	516668951	0	0
RvalidKnown_A	516776511	516668951	0	0
WreadyKnown_A	516776511	516668951	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	60191372	0	0
T1	123408	136538	0	0
T2	201244	18999	0	0
T3	152621	20821	0	0
T4	190686	21351	0	0
T5	117968	15204	0	0
T6	419700	188411	0	0
T31	450550	55697	0	0
T32	68584	8207	0	0
T36	192070	22605	0	0
T47	325436	3461	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516776511	46174197	0	0
DepthKnown_A	516776511	516668951	0	0
RvalidKnown_A	516776511	516668951	0	0
WreadyKnown_A	516776511	516668951	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	46174197	0	0
T1	123408	118746	0	0
T2	201244	13944	0	0
T3	152621	15546	0	0
T4	190686	17449	0	0
T5	117968	11163	0	0
T6	419700	94692	0	0
T31	450550	44337	0	0
T32	68584	5668	0	0
T36	192070	17608	0	0
T47	325436	1868	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516776511	43293834	0	0
DepthKnown_A	516776511	516668951	0	0
RvalidKnown_A	516776511	516668951	0	0
WreadyKnown_A	516776511	516668951	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	43293834	0	0
T1	123408	162069	0	0
T2	201244	11159	0	0
T3	152621	9014	0	0
T4	190686	17622	0	0
T5	117968	7666	0	0
T6	419700	16057	0	0
T31	450550	24016	0	0
T32	68584	4375	0	0
T36	192070	12962	0	0
T47	325436	459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	516776511	36382400	0	0
DepthKnown_A	516776511	516668951	0	0
RvalidKnown_A	516776511	516668951	0	0
WreadyKnown_A	516776511	516668951	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	36382400	0	0
T1	123408	110976	0	0
T2	201244	10848	0	0
T3	152621	8739	0	0
T4	190686	17416	0	0
T5	117968	7420	0	0
T6	419700	14868	0	0
T31	450550	23253	0	0
T32	68584	4243	0	0
T36	192070	12614	0	0
T47	325436	351	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	516776511	516668951	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613015356	102774	0	0
DepthKnown_A	613015356	612891435	0	0
RvalidKnown_A	613015356	612891435	0	0
WreadyKnown_A	613015356	612891435	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	102774	0	0
T1	123408	27	0	0
T2	201244	94	0	0
T3	152621	26	0	0
T4	190686	53	0	0
T5	117968	25	0	0
T6	419700	91	0	0
T31	450550	78	0	0
T32	68584	15	0	0
T36	192070	74	0	0
T47	325436	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613015356	104069	0	0
DepthKnown_A	613015356	612891435	0	0
RvalidKnown_A	613015356	612891435	0	0
WreadyKnown_A	613015356	612891435	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	104069	0	0
T1	123408	27	0	0
T2	201244	94	0	0
T3	152621	26	0	0
T4	190686	53	0	0
T5	117968	25	0	0
T6	419700	91	0	0
T31	450550	78	0	0
T32	68584	15	0	0
T36	192070	74	0	0
T47	325436	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613015356	51692	0	0
DepthKnown_A	613015356	612891435	0	0
RvalidKnown_A	613015356	612891435	0	0
WreadyKnown_A	613015356	612891435	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	51692	0	0
T2	201244	90	0	0
T3	152621	23	0	0
T4	190686	52	0	0
T5	117968	22	0	0
T6	419700	86	0	0
T31	450550	75	0	0
T32	68584	14	0	0
T36	192070	72	0	0
T45	151247	12	0	0
T47	325436	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613015356	51692	0	0
DepthKnown_A	613015356	612891435	0	0
RvalidKnown_A	613015356	612891435	0	0
WreadyKnown_A	613015356	612891435	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	51692	0	0
T2	201244	90	0	0
T3	152621	23	0	0
T4	190686	52	0	0
T5	117968	22	0	0
T6	419700	86	0	0
T31	450550	75	0	0
T32	68584	14	0	0
T36	192070	72	0	0
T45	151247	12	0	0
T47	325436	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613015356	51082	0	0
DepthKnown_A	613015356	612891435	0	0
RvalidKnown_A	613015356	612891435	0	0
WreadyKnown_A	613015356	612891435	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	51082	0	0
T1	123408	27	0	0
T2	201244	4	0	0
T3	152621	3	0	0
T4	190686	1	0	0
T5	117968	3	0	0
T6	419700	5	0	0
T31	450550	3	0	0
T32	68584	1	0	0
T36	192070	2	0	0
T45	0	29	0	0
T47	325436	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	613015356	52377	0	0
DepthKnown_A	613015356	612891435	0	0
RvalidKnown_A	613015356	612891435	0	0
WreadyKnown_A	613015356	612891435	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	52377	0	0
T1	123408	27	0	0
T2	201244	4	0	0
T3	152621	3	0	0
T4	190686	1	0	0
T5	117968	3	0	0
T6	419700	5	0	0
T31	450550	3	0	0
T32	68584	1	0	0
T36	192070	2	0	0
T45	0	29	0	0
T47	325436	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	613015356	612891435	0	0
T1	123408	123396	0	0
T2	201244	201138	0	0
T3	152621	152570	0	0
T4	190686	190628	0	0
T5	117968	117910	0	0
T6	419700	419668	0	0
T31	450550	450386	0	0
T32	68584	68526	0	0
T36	192070	191972	0	0
T47	325436	325381	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T36	1	1	0	0
T47	1	1	0	0