Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_o.a_ready	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T247,*T788,*T76	Yes	T247,T788,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T45,*T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T795,T796	Yes	T80,T795,T796	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T795,T796	Yes	T80,T795,T796	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T198,T134,T303	Yes	T198,T134,T303	OUTPUT
intr_tx_empty_o	Yes	Yes	T198,T134,T303	Yes	T198,T134,T303	OUTPUT
intr_rx_watermark_o	Yes	Yes	T198,T134,T303	Yes	T198,T134,T303	OUTPUT
intr_tx_done_o	Yes	Yes	T278,T198,T134	Yes	T278,T198,T134	OUTPUT
intr_rx_overflow_o	Yes	Yes	T278,T198,T134	Yes	T278,T198,T134	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_o.a_ready	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T247,*T788,*T76	Yes	T247,T788,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T45,*T46	Yes	T1,T45,T46	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T235,T49	Yes	T80,T235,T49	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T235,T49	Yes	T80,T235,T49	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T198,T303,T292	Yes	T198,T303,T292	OUTPUT
intr_tx_empty_o	Yes	Yes	T198,T303,T292	Yes	T198,T303,T292	OUTPUT
intr_rx_watermark_o	Yes	Yes	T198,T303,T292	Yes	T198,T303,T292	OUTPUT
intr_tx_done_o	Yes	Yes	T278,T198,T329	Yes	T278,T198,T329	OUTPUT
intr_rx_overflow_o	Yes	Yes	T278,T198,T329	Yes	T278,T198,T329	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T194,T330,T42	Yes	T194,T330,T42	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T194,T330,T42	Yes	T194,T330,T42	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	INPUT
tl_o.a_ready	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T194,T330,T42	Yes	T194,T330,T42	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T132,*T133	Yes	T76,T132,T133	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T194,*T330,*T42	Yes	T194,T330,T42	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T795,T235	Yes	T80,T795,T235	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T795,T235	Yes	T80,T795,T235	OUTPUT
cio_rx_i	Yes	Yes	T34,T194,T330	Yes	T34,T194,T13	INPUT
cio_tx_o	Yes	Yes	T194,T330,T331	Yes	T194,T330,T331	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T194,T330,T313	Yes	T194,T330,T313	OUTPUT
intr_tx_empty_o	Yes	Yes	T194,T330,T313	Yes	T194,T330,T313	OUTPUT
intr_rx_watermark_o	Yes	Yes	T194,T330,T313	Yes	T194,T330,T313	OUTPUT
intr_tx_done_o	Yes	Yes	T194,T330,T313	Yes	T194,T330,T313	OUTPUT
intr_rx_overflow_o	Yes	Yes	T194,T330,T313	Yes	T194,T330,T313	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T134,T42,T327	Yes	T134,T42,T327	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T134,T42,T327	Yes	T134,T42,T327	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	INPUT
tl_o.a_ready	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T134,T42,T327	Yes	T134,T42,T327	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T132,*T133	Yes	T76,T132,T133	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T134,*T42,*T327	Yes	T134,T42,T327	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T235,T49	Yes	T80,T235,T49	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T235,T49	Yes	T80,T235,T49	OUTPUT
cio_rx_i	Yes	Yes	T134,T327,T332	Yes	T134,T327,T332	INPUT
cio_tx_o	Yes	Yes	T134,T327,T332	Yes	T134,T327,T332	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T134,T327,T313	Yes	T134,T327,T313	OUTPUT
intr_tx_empty_o	Yes	Yes	T134,T327,T313	Yes	T134,T327,T313	OUTPUT
intr_rx_watermark_o	Yes	Yes	T134,T327,T313	Yes	T134,T327,T313	OUTPUT
intr_tx_done_o	Yes	Yes	T134,T327,T313	Yes	T134,T327,T313	OUTPUT
intr_rx_overflow_o	Yes	Yes	T134,T327,T313	Yes	T134,T327,T313	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	INPUT
tl_o.a_ready	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T72,T77	Yes	T70,T72,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T132,*T133	Yes	T76,T132,T133	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T72,T77	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T15,*T315	Yes	T4,T15,T315	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T796,T235	Yes	T80,T796,T235	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T796,T235	Yes	T80,T796,T235	OUTPUT
cio_rx_i	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	INPUT
cio_tx_o	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
intr_tx_empty_o	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
intr_rx_watermark_o	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
intr_tx_done_o	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
intr_rx_overflow_o	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_break_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_timeout_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T313,T314,T319	Yes	T313,T314,T319	OUTPUT

*Tests covering at least one bit in the range