Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T87,T203,T204	Yes	T87,T203,T204	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T84,T87,T203	Yes	T84,T87,T203	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T75,T184,T113	Yes	T75,T184,T113	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T75,T184,T113	Yes	T75,T184,T113	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T59,T60,T84	Yes	T59,T60,T84	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T2,T31,T36	Yes	T2,T3,T32	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T47,T64,T65	Yes	T47,T64,T65	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T31,T36	Yes	T2,T3,T32	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T2,T31,T36	Yes	T2,T3,T32	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T47,T64,T65	Yes	T47,T64,T65	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T2,T31,T36	Yes	T2,T3,T32	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T47,T64,T65	Yes	T47,T64,T65	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T47,T64,T65	Yes	T47,T64,T65	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T47,T64,T65	Yes	T47,T64,T65	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T47,T73,T74	Yes	T47,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T47,*T64,*T65	Yes	T47,T64,T65	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T47,T64,T65	Yes	T47,T64,T65	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T70,T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T77	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T77	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T113,*T70,*T71	Yes	T113,T70,T71	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T246,T247,T248	Yes	T246,T247,T248	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T246,T247,T248	Yes	T246,T247,T248	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T246,T247,T248	Yes	T246,T247,T248	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T246,T247,T248	Yes	T246,T247,T248	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T246,T247,T248	Yes	T246,T247,T248	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T246,*T247,*T248	Yes	T246,T247,T248	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T246,T247,T248	Yes	T246,T247,T248	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T2,T3,T32	Yes	T2,T31,T36	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T246,T247,T248	Yes	T246,T247,T248	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T246,T247,T248	Yes	T246,T247,T248	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T32	Yes	T2,T31,T36	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T246,*T247,*T248	Yes	T246,T247,T248	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T32	Yes	T2,T31,T36	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T246,T247,T248	Yes	T246,T247,T248	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T47,T45	Yes	T1,T47,T45	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T1,T45,T7	Yes	T1,T45,T7	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T49,T394,T50	Yes	T49,T394,T50	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T49,T394,T50	Yes	T49,T394,T50	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T49,T394,T50	Yes	T49,T394,T50	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T49,T394,T50	Yes	T49,T394,T50	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T49,T394,T50	Yes	T49,T394,T50	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T395,T396,T397	Yes	T395,T396,T397	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T49,T50,T51	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T395,T396,T397	Yes	T49,T50,T395	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T77	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T77	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T394,*T395,*T397	Yes	T394,T395,T396	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T49,T394,T50	Yes	T49,T394,T50	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T84,T87,T203	Yes	T84,T87,T203	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T12,T179,T182	Yes	T12,T179,T182	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T70,T77,T138	Yes	T70,T77,T138	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T70,T72,T77	Yes	T70,T77,T138	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T140,*T11,*T12	Yes	T140,T11,T12	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T140,T11,T12	Yes	T140,T11,T12	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T140,*T34,*T42	Yes	T140,T34,T42	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T140,T34,T42	Yes	T140,T34,T42	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T76,*T132,*T133	Yes	T76,T132,T133	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	INPUT
tl_usbdev_i.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T76,*T132,*T133	Yes	T76,T132,T133	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T16,*T387,*T17	Yes	T16,T387,T17	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T16,T387,T17	Yes	T16,T387,T17	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T31	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T31	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T113,*T70,*T71	Yes	T113,T70,T71	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T31	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T778,T779,T780	Yes	T778,T779,T780	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	INPUT
tl_hmac_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	INPUT
tl_hmac_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T1,*T45,*T778	Yes	T1,T45,T778	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T1,T45,T778	Yes	T1,T45,T778	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T140,T275,T88	Yes	T140,T275,T88	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T140,T275,T88	Yes	T140,T275,T88	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T275,T205,T444	Yes	T275,T205,T444	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	INPUT
tl_kmac_i.d_error	Yes	Yes	T70,T72,T138	Yes	T70,T72,T138	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	INPUT
tl_kmac_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T70,*T77,*T138	Yes	T70,T71,T72	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T31,*T92,*T140	Yes	T31,T92,T140	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T234,T103,T86	Yes	T234,T103,T86	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T234,T103,T86	Yes	T234,T103,T86	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T234,T112,T103	Yes	T234,T112,T103	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T234,T103,T86	Yes	T234,T103,T86	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T234,T112,T103	Yes	T234,T112,T103	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T113,T70,T72	Yes	T113,T70,T72	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T234,T112,T103	Yes	T234,T112,T103	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T234,T112,T103	Yes	T234,T112,T103	INPUT
tl_aes_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T234,T112,T103	Yes	T234,T112,T103	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T234,T112,T103	Yes	T234,T112,T103	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T112,T103,T86	Yes	T234,T112,T103	INPUT
tl_aes_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T234,*T112,*T103	Yes	T234,T112,T103	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T234,T112,T103	Yes	T234,T112,T103	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T95,T111,T112	Yes	T95,T111,T112	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T95,*T111,*T112	Yes	T45,T95,T46	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T32,T112,T85	Yes	T32,T112,T85	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T77	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T32,T112,T85	Yes	T32,T112,T85	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T2,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T32,*T112,*T85	Yes	T32,T112,T85	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T77	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T112,*T85,*T88	Yes	T112,T85,T88	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	INPUT
tl_edn1_i.d_error	Yes	Yes	T70,T72,T77	Yes	T70,T72,T77	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	INPUT
tl_edn1_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T112,*T85,*T88	Yes	T112,T85,T88	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T112,T85,T88	Yes	T112,T85,T88	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T5	Yes	T3,T4,T5	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T74,*T75,*T184	Yes	T74,T75,T184	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_otbn_i.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_otbn_i.d_sink	Yes	Yes	T70,T77,T138	Yes	T70,T71,T77	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T184	Yes	T74,T75,T184	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T1,*T45,*T46	Yes	T1,T45,T46	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	INPUT
tl_keymgr_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T77	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T31,T92,T140	Yes	T31,T92,T140	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T31,*T45,*T92	Yes	T31,T45,T92	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T31,T45,T92	Yes	T31,T45,T92	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T247,*T70,*T71	Yes	T247,T70,T71	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T247,T70,T71	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T437,*T438,*T70	Yes	T437,T438,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T70,T71,T138	Yes	T70,T71,T138	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T164,T165,T298	Yes	T164,T165,T298	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T43,T104	Yes	T1,T45,T46	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T1,T43,T104	Yes	T1,T45,T46	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T437,T438,T70	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T70,T71,T138	Yes	T70,T71,T138	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T104,*T161,*T162	Yes	T104,T161,T162	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T31	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range