Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T84,T87,T203	Yes	T84,T87,T203	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_uart0_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_uart0_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T247,*T788,*T76	Yes	T247,T788,T76	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T1,*T45,*T46	Yes	T1,T45,T46	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T194,T330,T42	Yes	T194,T330,T42	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T194,T330,T42	Yes	T194,T330,T42	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	INPUT
tl_uart1_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T194,T330,T42	Yes	T194,T330,T42	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	INPUT
tl_uart1_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T76,*T132,*T133	Yes	T76,T132,T133	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T194,*T330,*T42	Yes	T194,T330,T42	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T194,T235,T330	Yes	T194,T235,T330	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T134,T42,T327	Yes	T134,T42,T327	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T134,T42,T327	Yes	T134,T42,T327	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	INPUT
tl_uart2_i.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T134,T42,T327	Yes	T134,T42,T327	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	INPUT
tl_uart2_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T76,*T132,*T133	Yes	T76,T132,T133	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T134,*T42,*T327	Yes	T134,T42,T327	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T134,T235,T42	Yes	T134,T235,T42	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	INPUT
tl_uart3_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	INPUT
tl_uart3_i.d_sink	Yes	Yes	T70,T72,T77	Yes	T70,T72,T77	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T76,*T132,*T133	Yes	T76,T132,T133	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T70,T72,T77	Yes	T70,T71,T72	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T4,*T15,*T315	Yes	T4,T15,T315	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T4,T15,T315	Yes	T4,T15,T315	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T245,T42,T180	Yes	T245,T42,T180	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T245,T42,T180	Yes	T245,T42,T180	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T245,T235,T42	Yes	T245,T235,T42	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T245,T235,T42	Yes	T245,T235,T42	INPUT
tl_i2c0_i.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T245,T42,T180	Yes	T245,T42,T180	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T245,T235,T42	Yes	T245,T235,T42	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T245,T235,T42	Yes	T245,T235,T42	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T77	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T245,*T42,*T180	Yes	T245,T42,T180	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T245,T235,T42	Yes	T245,T235,T42	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T245,T195,T42	Yes	T245,T195,T42	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T245,T195,T42	Yes	T245,T195,T42	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T245,T195,T235	Yes	T245,T195,T235	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T245,T195,T235	Yes	T245,T195,T235	INPUT
tl_i2c1_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T138	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T245,T195,T42	Yes	T245,T195,T42	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T245,T195,T235	Yes	T245,T195,T235	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T245,T195,T235	Yes	T245,T195,T235	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T138	Yes	T70,T71,T72	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T138	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T245,*T195,*T42	Yes	T245,T195,T42	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T245,T195,T235	Yes	T245,T195,T235	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T197,T245,T328	Yes	T197,T245,T328	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T197,T245,T328	Yes	T197,T245,T328	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T197,T245,T235	Yes	T197,T245,T235	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T197,T245,T235	Yes	T197,T245,T235	INPUT
tl_i2c2_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T197,T245,T328	Yes	T197,T245,T328	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T197,T245,T235	Yes	T197,T245,T235	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T197,T245,T235	Yes	T197,T245,T235	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T197,*T245,*T328	Yes	T197,T245,T328	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T197,T245,T235	Yes	T197,T245,T235	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T140,T42,T180	Yes	T140,T42,T180	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T140,T42,T180	Yes	T140,T42,T180	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T140,T42,T49	Yes	T140,T42,T49	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T140,T42,T49	Yes	T140,T42,T49	INPUT
tl_pattgen_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T140,T42,T180	Yes	T140,T42,T180	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T42,T180	Yes	T140,T42,T49	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T140,T42,T180	Yes	T140,T42,T49	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T140,*T42,*T180	Yes	T140,T42,T180	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T140,T42,T49	Yes	T140,T42,T49	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T135,T196,T42	Yes	T135,T196,T42	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T135,T196,T42	Yes	T135,T196,T42	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T135,T196,T42	Yes	T135,T196,T42	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T135,T196,T42	Yes	T135,T196,T42	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T77	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T135,T196,T42	Yes	T135,T196,T42	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T135,T196,T42	Yes	T135,T196,T42	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T135,T196,T42	Yes	T135,T196,T42	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T135,*T196,*T42	Yes	T135,T196,T42	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T135,T196,T42	Yes	T135,T196,T42	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T5,T14,T245	Yes	T5,T14,T245	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T14,T245	Yes	T5,T14,T23	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T5,T14,T245	Yes	T5,T14,T23	INPUT
tl_gpio_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T5,T15,T140	Yes	T5,T15,T140	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T5,T15,T140	Yes	T5,T15,T140	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T5,T15,T140	Yes	T5,T15,T140	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T5,T15,T140	Yes	T5,T15,T140	INPUT
tl_spi_device_i.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T15,T140,T64	Yes	T15,T140,T64	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T15,T140	Yes	T5,T15,T140	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T5,T15,T140	Yes	T15,T140,T64	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T5,*T15,*T140	Yes	T5,T15,T140	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T5,T15,T140	Yes	T5,T15,T140	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T140,T242,T243	Yes	T140,T242,T243	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T140,T242,T243	Yes	T140,T242,T243	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T140,T242,T243	Yes	T140,T242,T243	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T140,T242,T243	Yes	T140,T242,T243	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T140,T242,T243	Yes	T140,T242,T243	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T242,T243	Yes	T140,T242,T243	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T242,T243,T799	Yes	T140,T242,T243	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T140,*T242,*T243	Yes	T140,T242,T243	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T140,T242,T243	Yes	T140,T242,T243	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T36	Yes	T1,T3,T36	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T3,T36	Yes	T1,T3,T36	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T1,T3,T36	Yes	T1,T3,T36	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T1,T3,T36	Yes	T1,T3,T36	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T36	Yes	T1,T3,T36	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T36	Yes	T1,T3,T36	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T36	Yes	T1,T3,T36	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T36	Yes	T1,T3,T36	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T1,T3,T36	Yes	T1,T3,T36	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T70,T71,T138	Yes	T70,T71,T72	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T138	Yes	T70,T71,T72	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T778,T15	Yes	T4,T778,T15	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T778,T15	Yes	T4,T778,T15	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T15,T198	Yes	T4,T15,T198	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T73,T783,T784	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T778,*T15	Yes	T4,T778,T15	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T77	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T32	Yes	T2,T3,T32	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T70,T72,T138	Yes	T70,T138,T139	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T72,T77	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T31,*T6,*T92	Yes	T31,T6,T92	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T2,T3,T32	Yes	T2,T31,T36	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T2,T3,T32	Yes	T2,T31,T36	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T72	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T70,*T71,T72	Yes	T70,T71,T72	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T32	Yes	T2,T31,T36	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T77,T138	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T6,T106	Yes	T2,T6,T106	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T248,*T299,*T300	Yes	T248,T299,T300	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T31	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T1,T2,T31	Yes	T1,T2,T31	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T114,T140	Yes	T1,T114,T140	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T114,T140	Yes	T1,T114,T140	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T31	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T45	Yes	T2,T3,T45	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T91	Yes	T2,T3,T45	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T104,T161,T162	Yes	T104,T161,T162	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T43,T104	Yes	T1,T45,T46	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T1,T43,T104	Yes	T1,T45,T46	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T104,*T161,*T162	Yes	T104,T161,T162	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T1,T45,T46	Yes	T1,T45,T46	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T31	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T2,T3,T31	Yes	T2,T3,T31	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T247	Yes	T74,T75,T247	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T45	Yes	T1,T3,T45	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T1,T3,T45	Yes	T1,T3,T45	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T1,T3,T45	Yes	T1,T3,T45	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T1,T3,T45	Yes	T1,T3,T45	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T91,T94	Yes	T3,T91,T94	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T45	Yes	T1,T3,T45	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T45	Yes	T1,T3,T45	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T246,T788,T789	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T45	Yes	T1,T3,T45	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T1,T3,T45	Yes	T1,T3,T45	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T36,T93,T94	Yes	T36,T93,T94	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T36,T93,T94	Yes	T36,T93,T94	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T36,T93,T94	Yes	T36,T93,T94	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T36,T93,T94	Yes	T36,T93,T94	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T36,T93,T94	Yes	T36,T93,T94	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T36,T93,T94	Yes	T36,T93,T94	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T36,T93,T94	Yes	T36,T93,T94	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T76,*T132,*T133	Yes	T76,T132,T133	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T36,*T93,*T94	Yes	T36,T93,T94	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T36,T93,T94	Yes	T36,T93,T94	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T245,T100,T101	Yes	T245,T100,T101	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T245,T100,T101	Yes	T245,T100,T101	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T245,T100,T101	Yes	T245,T100,T101	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T245,T100,T101	Yes	T245,T100,T101	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T245,T100,T101	Yes	T245,T100,T101	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T245,T100,T101	Yes	T245,T100,T101	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T100,T101,T18	Yes	T245,T100,T101	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T245,*T100,*T101	Yes	T245,T100,T101	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T245,T100,T101	Yes	T245,T100,T101	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T64,*T65,*T73	Yes	T64,T65,T73	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T113,T70,T71	Yes	T113,T70,T71	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T2,T31	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T77	Yes	T70,T71,T72	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T70,T71,T77	Yes	T70,T71,T77	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T113,*T70,*T71	Yes	T113,T70,T71	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range