Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3517027	1			T79	1004		T80	3237		T81	85
values[2]	704325	1			T79	241		T80	315		T81	43
values[3]	97567	1			T79	2		T137	143		T251	119
values[4]	51370	1			T137	133		T251	55		T565	192
values[5]	34452	1			T137	142		T251	24		T565	111
values[6]	25596	1			T137	156		T251	7		T565	74
values[7]	20807	1			T137	129		T251	23		T565	57
values[8]	17779	1			T137	113		T251	8		T565	42
values[9]	15714	1			T137	114		T251	5		T565	38
values[10]	14252	1			T137	116		T251	8		T565	38
values[11]	12760	1			T137	148		T565	42		T552	58
values[12]	12026	1			T137	146		T565	37		T552	36
values[13]	11571	1			T137	166		T565	37		T552	47
values[14]	10936	1			T137	149		T565	20		T552	36
values[15]	10490	1			T137	116		T565	13		T552	26
values[16]	10117	1			T137	158		T565	26		T552	24
values[17]	9825	1			T137	128		T565	20		T552	25
values[18]	9645	1			T137	121		T565	20		T552	20
values[19]	9501	1			T137	125		T565	18		T552	21
values[20]	9229	1			T137	102		T565	26		T552	32
values[21]	8764	1			T137	124		T565	35		T552	22
values[22]	8335	1			T137	108		T565	20		T552	18
values[23]	8132	1			T137	102		T565	21		T552	17
values[24]	7867	1			T137	97		T565	22		T552	13
values[25]	7547	1			T137	73		T565	12		T552	5
values[26]	7141	1			T137	70		T565	10		T552	11
values[27]	6756	1			T137	66		T565	13		T552	14
values[28]	6446	1			T137	82		T565	10		T552	15
values[29]	6308	1			T137	84		T565	8		T552	20
values[30]	5855	1			T137	82		T565	3		T552	16
values[31]	5362	1			T137	66		T565	3		T552	13
values[32]	4975	1			T137	55		T565	7		T552	5
values[33]	4525	1			T137	41		T565	15		T552	3
values[34]	4405	1			T137	31		T565	20		T552	7
values[35]	4191	1			T137	42		T565	13		T552	12
values[36]	3956	1			T137	32		T565	11		T552	9
values[37]	3806	1			T137	31		T565	8		T552	9
values[38]	3681	1			T137	21		T565	8		T552	1
values[39]	3628	1			T137	7		T565	11		T939	2
values[40]	3332	1			T137	5		T565	8		T939	2
values[41]	3346	1			T137	10		T565	9		T939	3
values[42]	3249	1			T137	9		T565	12		T939	2
values[43]	3204	1			T137	12		T565	7		T939	2
values[44]	3151	1			T137	13		T565	12		T939	3
values[45]	3097	1			T137	14		T565	7		T939	2
values[46]	2913	1			T137	9		T565	12		T939	2
values[47]	2911	1			T137	9		T565	14		T939	2
values[48]	2962	1			T137	12		T565	6		T939	2
values[49]	2930	1			T137	3		T565	7		T939	2
values[50]	2962	1			T137	1		T565	6		T939	2
values[51]	2884	1			T137	4		T565	12		T939	2
values[52]	2845	1			T137	4		T565	11		T939	2
values[53]	2769	1			T137	2		T565	10		T939	2
values[54]	2673	1			T137	2		T565	4		T939	2
values[55]	2629	1			T137	4		T565	5		T939	2
values[56]	2544	1			T137	4		T565	4		T939	2
values[57]	2514	1			T137	1		T565	4		T939	2
values[58]	2461	1			T565	3		T939	2		T556	6
values[59]	2500	1			T565	2		T939	2		T556	4
values[60]	2457	1			T565	3		T939	2		T556	4
values[61]	2633	1			T565	3		T939	2		T556	5
values[62]	3768	1			T565	6		T939	2		T556	11
values[63]	10076	1			T565	13		T939	2		T556	48
values[64]	242967	1			T565	117		T939	393		T556	214

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4505550	1			T79	1192		T80	3691		T81	113
values[2]	768708	1			T79	295		T80	338		T81	38
values[3]	81049	1			T79	10		T80	34		T81	2
values[4]	14169	1			T80	1		T137	9		T251	24
values[5]	5319	1			T137	2		T251	26		T565	1
values[6]	3115	1			T251	14		T565	2		T421	2
values[7]	2343	1			T251	5		T565	4		T421	1
values[8]	2010	1			T251	7		T565	2		T939	1
values[9]	1684	1			T251	6		T565	2		T939	1
values[10]	1462	1			T251	6		T565	3		T939	1
values[11]	1370	1			T251	4		T565	11		T939	1
values[12]	1235	1			T251	6		T565	11		T939	1
values[13]	1123	1			T251	3		T565	19		T939	1
values[14]	956	1			T251	4		T565	17		T939	1
values[15]	956	1			T251	6		T565	10		T939	1
values[16]	884	1			T251	2		T565	10		T939	1
values[17]	888	1			T251	1		T565	3		T939	1
values[18]	800	1			T251	5		T939	1		T556	3
values[19]	725	1			T251	2		T939	1		T556	2
values[20]	719	1			T251	5		T939	1		T556	1
values[21]	675	1			T939	1		T556	1		T554	8
values[22]	612	1			T939	1		T556	1		T554	14
values[23]	589	1			T939	1		T556	1		T554	16
values[24]	607	1			T939	1		T556	2		T554	6
values[25]	612	1			T939	1		T556	1		T554	7
values[26]	644	1			T939	1		T556	1		T554	8
values[27]	606	1			T939	1		T556	1		T554	8
values[28]	541	1			T939	1		T556	1		T554	9
values[29]	575	1			T939	1		T556	1		T554	7
values[30]	570	1			T939	1		T556	1		T554	12
values[31]	547	1			T939	1		T556	1		T554	12
values[32]	514	1			T939	1		T556	2		T554	14
values[33]	483	1			T939	1		T556	6		T554	16
values[34]	469	1			T939	1		T556	6		T554	14
values[35]	454	1			T939	1		T556	2		T554	14
values[36]	489	1			T939	1		T556	1		T554	16
values[37]	532	1			T939	1		T556	1		T554	15
values[38]	450	1			T939	1		T556	1		T554	6
values[39]	459	1			T939	1		T556	3		T554	7
values[40]	434	1			T939	1		T556	1		T554	9
values[41]	429	1			T939	1		T556	1		T554	3
values[42]	416	1			T939	1		T556	2		T554	5
values[43]	421	1			T939	1		T556	1		T554	2
values[44]	420	1			T939	1		T556	1		T554	3
values[45]	396	1			T939	1		T556	1		T554	3
values[46]	414	1			T939	1		T556	1		T554	5
values[47]	435	1			T939	1		T556	2		T554	5
values[48]	412	1			T939	1		T556	3		T554	5
values[49]	400	1			T939	1		T556	1		T554	8
values[50]	366	1			T939	1		T556	1		T554	8
values[51]	394	1			T939	1		T556	1		T554	11
values[52]	375	1			T939	1		T556	1		T554	7
values[53]	352	1			T939	1		T556	1		T554	5
values[54]	356	1			T939	1		T556	3		T554	5
values[55]	375	1			T939	1		T556	1		T554	12
values[56]	356	1			T939	1		T556	1		T554	7
values[57]	361	1			T939	1		T556	1		T554	5
values[58]	374	1			T939	1		T556	1		T554	6
values[59]	345	1			T939	2		T556	1		T554	5
values[60]	336	1			T939	1		T556	1		T554	5
values[61]	380	1			T939	1		T556	3		T554	4
values[62]	651	1			T939	1		T556	3		T554	7
values[63]	2663	1			T939	1		T556	26		T554	50
values[64]	27965	1			T939	203		T556	86		T554	100

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	553072	1			T79	9		T80	585		T81	1
values[2]	2489332	1			T79	999		T80	2893		T81	58
values[3]	1115760	1			T79	315		T80	446		T81	34
values[4]	134073	1			T80	1		T137	247		T251	188
values[5]	69211	1			T137	188		T251	80		T565	238
values[6]	44948	1			T137	157		T251	20		T565	107
values[7]	33263	1			T137	146		T251	7		T565	97
values[8]	25833	1			T137	160		T251	11		T565	73
values[9]	21636	1			T137	123		T251	4		T565	77
values[10]	19091	1			T137	144		T251	2		T565	48
values[11]	17401	1			T137	143		T251	1		T565	62
values[12]	15851	1			T137	120		T251	3		T565	47
values[13]	14607	1			T137	160		T251	4		T565	38
values[14]	13549	1			T137	124		T251	10		T565	20
values[15]	13425	1			T137	121		T251	13		T565	26
values[16]	12936	1			T137	137		T251	8		T565	18
values[17]	12054	1			T137	145		T251	5		T565	16
values[18]	11499	1			T137	153		T251	2		T565	10
values[19]	11123	1			T137	142		T251	11		T565	9
values[20]	10542	1			T137	130		T251	6		T565	8
values[21]	10256	1			T137	161		T565	7		T552	19
values[22]	9854	1			T137	115		T565	4		T552	32
values[23]	9445	1			T137	106		T565	7		T552	42
values[24]	9211	1			T137	104		T565	5		T552	47
values[25]	8989	1			T137	107		T565	11		T552	38
values[26]	8647	1			T137	124		T565	9		T552	36
values[27]	7906	1			T137	129		T565	14		T552	29
values[28]	7494	1			T137	102		T565	4		T552	27
values[29]	6994	1			T137	94		T565	5		T552	12
values[30]	6508	1			T137	77		T565	10		T552	27
values[31]	6177	1			T137	51		T565	18		T552	11
values[32]	5766	1			T137	41		T565	17		T552	9
values[33]	5449	1			T137	16		T565	10		T552	13
values[34]	5078	1			T137	18		T565	7		T552	10
values[35]	4698	1			T137	19		T565	5		T552	3
values[36]	4433	1			T137	16		T565	11		T552	3
values[37]	4235	1			T137	11		T565	10		T939	2
values[38]	4007	1			T137	6		T565	14		T939	2
values[39]	3803	1			T137	16		T565	9		T939	2
values[40]	3704	1			T137	15		T565	4		T939	2
values[41]	3594	1			T137	23		T565	8		T939	2
values[42]	3384	1			T137	7		T565	11		T939	2
values[43]	3398	1			T137	8		T565	17		T939	2
values[44]	3391	1			T137	11		T565	5		T939	2
values[45]	3333	1			T137	3		T565	12		T939	2
values[46]	3304	1			T137	4		T565	14		T939	2
values[47]	3259	1			T137	3		T565	10		T939	2
values[48]	3092	1			T137	9		T565	10		T939	2
values[49]	3134	1			T137	3		T565	12		T939	2
values[50]	3046	1			T137	2		T565	8		T939	2
values[51]	2934	1			T137	3		T565	4		T939	2
values[52]	2929	1			T137	1		T565	5		T939	2
values[53]	2924	1			T137	1		T565	9		T939	2
values[54]	2882	1			T137	6		T565	16		T939	2
values[55]	2901	1			T137	3		T565	12		T939	2
values[56]	2826	1			T137	2		T565	12		T939	2
values[57]	2747	1			T137	6		T565	7		T939	2
values[58]	2589	1			T137	1		T565	4		T939	2
values[59]	2639	1			T137	2		T565	8		T939	2
values[60]	2625	1			T565	8		T939	2		T556	6
values[61]	2737	1			T565	2		T939	2		T556	9
values[62]	3490	1			T565	6		T939	2		T556	13
values[63]	8445	1			T565	9		T939	3		T556	32
values[64]	233756	1			T565	94		T939	380		T556	123