Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1811044	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

39207353

1

T1

6062

T2

4081

T3

5218

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28457421	1			T1	1034		T2	1281		T3	2093
values[0x0]	11037138	1			T1	5028		T2	2800		T3	3125
values[0x1]	1523838	1			T1	94		T2	202		T3	367

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	503397	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40515000

1

T1

6156

T2

4283

T3

5585

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19489517	1			T1	3079		T2	2142		T3	2793
valid_sources[0x01]	19487287	1			T1	3077		T2	2141		T3	2792
valid_sources[0x02]	33451	1			T746	512		T156	251		T157	124
valid_sources[0x03]	32181	1			T746	256		T156	250		T157	207
valid_sources[0x04]	33888	1			T56	2		T746	384		T156	244
valid_sources[0x05]	32514	1			T56	1		T209	2		T746	128
valid_sources[0x06]	33163	1			T209	3		T746	512		T156	222
valid_sources[0x07]	33395	1			T56	1		T746	896		T156	238
valid_sources[0x08]	32785	1			T56	1		T965	1		T746	508
valid_sources[0x09]	32843	1			T56	1		T746	512		T156	254
valid_sources[0x0a]	32271	1			T746	384		T156	232		T157	166
valid_sources[0x0b]	33095	1			T746	384		T156	258		T157	195
valid_sources[0x0c]	32933	1			T965	1		T746	384		T156	258
valid_sources[0x0d]	32554	1			T746	256		T156	271		T157	206
valid_sources[0x0e]	32476	1			T56	1		T209	3		T746	128
valid_sources[0x0f]	32751	1			T746	640		T156	250		T157	158
valid_sources[0x10]	32702	1			T208	1		T746	384		T156	231
valid_sources[0x11]	32597	1			T209	2		T746	128		T156	264
valid_sources[0x12]	32313	1			T208	4		T209	1		T746	256
valid_sources[0x13]	32281	1			T208	1		T209	1		T746	128
valid_sources[0x14]	32219	1			T746	128		T156	219		T157	202
valid_sources[0x15]	32488	1			T156	247		T157	175		T396	80
valid_sources[0x16]	32536	1			T746	256		T156	232		T157	187
valid_sources[0x17]	34397	1			T209	3		T746	640		T156	242
valid_sources[0x18]	33471	1			T746	768		T156	250		T157	149
valid_sources[0x19]	32641	1			T208	2		T209	1		T746	128
valid_sources[0x1a]	32540	1			T208	1		T746	512		T156	219
valid_sources[0x1b]	32587	1			T209	2		T746	256		T156	232
valid_sources[0x1c]	32278	1			T56	4		T156	254		T157	191
valid_sources[0x1d]	32713	1			T56	9		T208	1		T746	512
valid_sources[0x1e]	32396	1			T209	2		T746	384		T156	259
valid_sources[0x1f]	33108	1			T208	3		T965	2		T746	128
valid_sources[0x20]	32610	1			T746	256		T156	264		T157	151

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27943682

1

T1

1034

T2

1281

T3

2093

values[0x0]

all_enables

biggest_size

10984637

1

T1

5028

T2

2800

T3

3125

values[0x1]

all_enables

biggest_size

279034

1

T73

16

T82

17

T56

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2712851	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

428309

1

T79

7

T80

467

T81

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1061926	1			T79	27		T80	1191		T81	40
values[0x0]	1016146	1			T79	4		T80	1143		T81	47
values[0x1]	1063088	1			T79	25		T80	1216		T81	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2101043	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1040117

1

T79

18

T80

1148

T81

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49415	1			T80	52		T81	2		T137	16
valid_sources[0x01]	49165	1			T80	38		T137	17		T251	151
valid_sources[0x02]	48806	1			T79	1		T80	100		T137	17
valid_sources[0x03]	47592	1			T79	2		T80	84		T81	3
valid_sources[0x04]	48618	1			T79	3		T80	27		T81	2
valid_sources[0x05]	49279	1			T80	36		T137	16		T251	139
valid_sources[0x06]	49083	1			T79	1		T80	86		T81	1
valid_sources[0x07]	49782	1			T79	1		T80	2		T81	2
valid_sources[0x08]	48691	1			T80	1		T81	2		T137	28
valid_sources[0x09]	49276	1			T79	3		T80	36		T81	2
valid_sources[0x0a]	48770	1			T79	1		T80	29		T137	22
valid_sources[0x0b]	48516	1			T80	144		T137	27		T251	93
valid_sources[0x0c]	48896	1			T80	28		T81	3		T137	17
valid_sources[0x0d]	49685	1			T79	1		T80	54		T81	3
valid_sources[0x0e]	48649	1			T79	2		T80	13		T137	13
valid_sources[0x0f]	48994	1			T80	119		T81	2		T137	24
valid_sources[0x10]	48913	1			T80	65		T81	3		T137	29
valid_sources[0x11]	48823	1			T79	1		T80	40		T81	1
valid_sources[0x12]	49039	1			T80	6		T137	26		T251	114
valid_sources[0x13]	49819	1			T80	96		T81	7		T137	30
valid_sources[0x14]	49457	1			T79	1		T80	107		T81	2
valid_sources[0x15]	49035	1			T79	1		T80	70		T137	33
valid_sources[0x16]	48868	1			T80	74		T81	1		T137	24
valid_sources[0x17]	48097	1			T80	79		T81	2		T137	19
valid_sources[0x18]	48990	1			T80	20		T81	2		T137	21
valid_sources[0x19]	49673	1			T79	1		T80	100		T81	3
valid_sources[0x1a]	50214	1			T79	1		T80	39		T81	1
valid_sources[0x1b]	49917	1			T79	1		T80	20		T81	2
valid_sources[0x1c]	48754	1			T79	2		T80	113		T81	3
valid_sources[0x1d]	49274	1			T79	1		T80	52		T81	2
valid_sources[0x1e]	49542	1			T80	84		T81	2		T137	14
valid_sources[0x1f]	50107	1			T79	1		T80	38		T137	22
valid_sources[0x20]	49541	1			T80	103		T137	22		T251	108

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45024

1

T79

2

T80

47

T137

43

values[0x0]

all_enables

biggest_size

338481

1

T79

2

T80

359

T81

14

values[0x1]

all_enables

biggest_size

44804

1

T79

3

T80

61

T81

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2887751	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469396

1

T79

4

T80

569

T81

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1149920	1			T79	31		T80	1387		T81	57
values[0x0]	1058817	1			T79	5		T80	1328		T81	42
values[0x1]	1148410	1			T79	29		T80	1347		T81	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2216077	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1141070

1

T79

22

T80

1376

T81

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52207	1			T79	1		T80	41		T81	4
valid_sources[0x01]	51218	1			T80	33		T137	22		T251	137
valid_sources[0x02]	52399	1			T79	2		T80	65		T81	1
valid_sources[0x03]	51922	1			T80	69		T81	8		T137	26
valid_sources[0x04]	51483	1			T80	31		T137	22		T251	106
valid_sources[0x05]	52414	1			T79	2		T80	52		T81	1
valid_sources[0x06]	53368	1			T80	43		T81	4		T137	15
valid_sources[0x07]	52047	1			T79	1		T80	21		T137	25
valid_sources[0x08]	53143	1			T80	19		T81	5		T137	23
valid_sources[0x09]	52290	1			T79	4		T80	78		T81	3
valid_sources[0x0a]	52482	1			T79	1		T80	15		T81	1
valid_sources[0x0b]	52936	1			T80	114		T81	4		T137	23
valid_sources[0x0c]	53041	1			T79	1		T80	37		T137	21
valid_sources[0x0d]	52956	1			T80	66		T81	7		T137	22
valid_sources[0x0e]	51887	1			T80	56		T81	3		T137	12
valid_sources[0x0f]	51530	1			T80	92		T137	13		T251	111
valid_sources[0x10]	51515	1			T80	68		T81	1		T137	24
valid_sources[0x11]	52403	1			T80	55		T81	1		T137	29
valid_sources[0x12]	51408	1			T80	18		T81	1		T137	30
valid_sources[0x13]	52588	1			T79	1		T80	59		T81	2
valid_sources[0x14]	52977	1			T79	1		T80	61		T137	18
valid_sources[0x15]	52553	1			T79	1		T80	41		T81	11
valid_sources[0x16]	53165	1			T80	45		T81	4		T137	25
valid_sources[0x17]	52864	1			T79	3		T80	145		T81	1
valid_sources[0x18]	51909	1			T80	34		T81	1		T137	31
valid_sources[0x19]	52986	1			T79	2		T80	93		T81	3
valid_sources[0x1a]	51699	1			T80	41		T81	6		T137	25
valid_sources[0x1b]	53066	1			T79	2		T80	80		T81	2
valid_sources[0x1c]	52161	1			T79	1		T80	58		T81	1
valid_sources[0x1d]	52921	1			T80	101		T137	15		T251	170
valid_sources[0x1e]	53420	1			T79	1		T80	51		T81	2
valid_sources[0x1f]	52639	1			T79	1		T80	83		T137	23
valid_sources[0x20]	51455	1			T80	69		T137	20		T251	117

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49545

1

T79

1

T80

59

T81

4

values[0x0]

all_enables

biggest_size

370471

1

T79

3

T80

458

T81

12

values[0x1]

all_enables

biggest_size

49380

1

T80

52

T81

2

T137

57

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2735517	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

431631

1

T79

5

T80

513

T81

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1072109	1			T79	30		T80	1351		T81	28
values[0x0]	1021778	1			T79	6		T80	1281		T81	31
values[0x1]	1073261	1			T79	24		T80	1289		T81	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2118437	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1048711

1

T79

16

T80

1274

T81

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49718	1			T79	1		T80	60		T137	24
valid_sources[0x01]	48189	1			T79	2		T80	66		T137	21
valid_sources[0x02]	50119	1			T80	69		T137	18		T251	127
valid_sources[0x03]	49985	1			T79	2		T80	64		T137	20
valid_sources[0x04]	48891	1			T79	4		T80	61		T81	3
valid_sources[0x05]	48587	1			T79	1		T80	24		T137	24
valid_sources[0x06]	48987	1			T79	2		T80	93		T137	18
valid_sources[0x07]	49397	1			T80	67		T137	16		T251	104
valid_sources[0x08]	49040	1			T80	54		T137	29		T251	77
valid_sources[0x09]	50271	1			T80	67		T137	18		T251	106
valid_sources[0x0a]	49747	1			T79	2		T80	16		T137	23
valid_sources[0x0b]	48737	1			T79	1		T80	83		T137	26
valid_sources[0x0c]	49364	1			T79	1		T80	39		T137	20
valid_sources[0x0d]	49894	1			T80	89		T81	1		T137	24
valid_sources[0x0e]	49315	1			T79	1		T80	35		T137	23
valid_sources[0x0f]	48580	1			T80	88		T137	15		T251	94
valid_sources[0x10]	48617	1			T79	1		T80	95		T137	20
valid_sources[0x11]	49093	1			T79	1		T80	30		T81	2
valid_sources[0x12]	49665	1			T79	1		T80	32		T81	1
valid_sources[0x13]	48813	1			T80	62		T81	6		T137	28
valid_sources[0x14]	49430	1			T79	1		T80	46		T81	6
valid_sources[0x15]	49778	1			T80	56		T137	20		T251	85
valid_sources[0x16]	50584	1			T79	1		T80	59		T81	6
valid_sources[0x17]	49583	1			T79	1		T80	125		T81	2
valid_sources[0x18]	49279	1			T79	3		T80	40		T137	22
valid_sources[0x19]	49875	1			T79	2		T80	51		T137	21
valid_sources[0x1a]	48919	1			T80	58		T137	25		T251	92
valid_sources[0x1b]	50112	1			T79	3		T80	36		T137	21
valid_sources[0x1c]	50965	1			T79	1		T80	86		T137	20
valid_sources[0x1d]	49940	1			T79	3		T80	55		T137	24
valid_sources[0x1e]	50364	1			T79	1		T80	114		T137	22
valid_sources[0x1f]	50482	1			T79	1		T80	104		T81	2
valid_sources[0x20]	49628	1			T80	80		T81	5		T137	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45310

1

T79

2

T80

55

T81

1

values[0x0]

all_enables

biggest_size

341157

1

T79

2

T80

405

T81

13

values[0x1]

all_enables

biggest_size

45164

1

T79

1

T80

53

T137

44