Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544495194	63102320	0	0
DepthKnown_A	544495194	544384849	0	0
RvalidKnown_A	544495194	544384849	0	0
WreadyKnown_A	544495194	544384849	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	63102320	0	0
T1	156491	11969	0	0
T2	71879	7366	0	0
T3	95939	10990	0	0
T4	227290	23269	0	0
T5	90936	10728	0	0
T6	262310	35195	0	0
T7	122253	135588	0	0
T8	262518	8298	0	0
T35	208471	19909	0	0
T87	100365	11143	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544495194	48953264	0	0
DepthKnown_A	544495194	544384849	0	0
RvalidKnown_A	544495194	544384849	0	0
WreadyKnown_A	544495194	544384849	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	48953264	0	0
T1	156491	8212	0	0
T2	71879	5599	0	0
T3	95939	8614	0	0
T4	227290	19356	0	0
T5	90936	8355	0	0
T6	262310	25210	0	0
T7	122253	117928	0	0
T8	262518	6422	0	0
T35	208471	14877	0	0
T87	100365	9027	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544495194	45893236	0	0
DepthKnown_A	544495194	544384849	0	0
RvalidKnown_A	544495194	544384849	0	0
WreadyKnown_A	544495194	544384849	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	45893236	0	0
T1	156491	6453	0	0
T2	71879	4398	0	0
T3	95939	5731	0	0
T4	227290	21583	0	0
T5	90936	6040	0	0
T6	262310	17727	0	0
T7	122253	158142	0	0
T8	262518	4955	0	0
T35	208471	11855	0	0
T87	100365	6233	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544495194	39000886	0	0
DepthKnown_A	544495194	544384849	0	0
RvalidKnown_A	544495194	544384849	0	0
WreadyKnown_A	544495194	544384849	0	0
gen_passthru_fifo.paramCheckPass	1034	1034	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	39000886	0	0
T1	156491	6156	0	0
T2	71879	4283	0	0
T3	95939	5585	0	0
T4	227290	21378	0	0
T5	90936	5907	0	0
T6	262310	17346	0	0
T7	122253	110262	0	0
T8	262518	4838	0	0
T35	208471	11544	0	0
T87	100365	6093	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544495194	544384849	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1034	1034	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628899305	90200	0	0
DepthKnown_A	628899305	628773273	0	0
RvalidKnown_A	628899305	628773273	0	0
WreadyKnown_A	628899305	628773273	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	90200	0	0
T1	156491	27	0	0
T2	71879	13	0	0
T3	95939	13	0	0
T4	227290	53	0	0
T5	90936	13	0	0
T6	262310	151	0	0
T7	122253	27	0	0
T8	262518	15	0	0
T35	208471	94	0	0
T87	100365	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628899305	92240	0	0
DepthKnown_A	628899305	628773273	0	0
RvalidKnown_A	628899305	628773273	0	0
WreadyKnown_A	628899305	628773273	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	92240	0	0
T1	156491	27	0	0
T2	71879	13	0	0
T3	95939	13	0	0
T4	227290	53	0	0
T5	90936	13	0	0
T6	262310	151	0	0
T7	122253	27	0	0
T8	262518	15	0	0
T35	208471	94	0	0
T87	100365	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628899305	53007	0	0
DepthKnown_A	628899305	628773273	0	0
RvalidKnown_A	628899305	628773273	0	0
WreadyKnown_A	628899305	628773273	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	53007	0	0
T1	156491	25	0	0
T2	71879	12	0	0
T3	95939	12	0	0
T4	227290	52	0	0
T5	90936	12	0	0
T6	262310	95	0	0
T7	122253	0	0	0
T8	262518	14	0	0
T35	208471	90	0	0
T87	100365	17	0	0
T122	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628899305	53007	0	0
DepthKnown_A	628899305	628773273	0	0
RvalidKnown_A	628899305	628773273	0	0
WreadyKnown_A	628899305	628773273	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	53007	0	0
T1	156491	25	0	0
T2	71879	12	0	0
T3	95939	12	0	0
T4	227290	52	0	0
T5	90936	12	0	0
T6	262310	95	0	0
T7	122253	0	0	0
T8	262518	14	0	0
T35	208471	90	0	0
T87	100365	17	0	0
T122	0	37	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628899305	37193	0	0
DepthKnown_A	628899305	628773273	0	0
RvalidKnown_A	628899305	628773273	0	0
WreadyKnown_A	628899305	628773273	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	37193	0	0
T1	156491	2	0	0
T2	71879	1	0	0
T3	95939	1	0	0
T4	227290	1	0	0
T5	90936	1	0	0
T6	262310	56	0	0
T7	122253	27	0	0
T8	262518	1	0	0
T35	208471	4	0	0
T87	100365	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628899305	39233	0	0
DepthKnown_A	628899305	628773273	0	0
RvalidKnown_A	628899305	628773273	0	0
WreadyKnown_A	628899305	628773273	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	39233	0	0
T1	156491	2	0	0
T2	71879	1	0	0
T3	95939	1	0	0
T4	227290	1	0	0
T5	90936	1	0	0
T6	262310	56	0	0
T7	122253	27	0	0
T8	262518	1	0	0
T35	208471	4	0	0
T87	100365	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628899305	628773273	0	0
T1	156491	156325	0	0
T2	71879	71817	0	0
T3	95939	95888	0	0
T4	227290	227239	0	0
T5	90936	90881	0	0
T6	262310	262200	0	0
T7	122253	122242	0	0
T8	262518	262408	0	0
T35	208471	208365	0	0
T87	100365	100314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T35	1	1	0	0
T87	1	1	0	0