Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.82	92.11		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T6,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T70,*T71	Yes	T55,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T82,T56	Yes	T73,T82,T56	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T7,T50	Yes	T4,T7,T50	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T55,*T260,*T261	Yes	T55,T260,T261	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T7	Yes	T4,T5,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T7	Yes	T4,T5,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T203,T57,T337	Yes	T203,T57,T337	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T790	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T790	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T203,T57,T337	Yes	T203,T57,T337	OUTPUT
cio_rx_i	Yes	Yes	T1,T4,T6	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T4,T7,T50	Yes	T4,T7,T50	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
intr_tx_empty_o	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
intr_rx_watermark_o	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
intr_tx_done_o	Yes	Yes	T4,T5,T160	Yes	T4,T5,T160	OUTPUT
intr_rx_overflow_o	Yes	Yes	T4,T5,T160	Yes	T4,T5,T160	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T6,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T7,T50	Yes	T5,T7,T50	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T7,T50	Yes	T5,T7,T50	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T70,*T71	Yes	T55,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T82,T56	Yes	T73,T82,T56	INPUT
tl_i.a_valid	Yes	Yes	T5,T7,T50	Yes	T5,T7,T50	INPUT
tl_o.a_ready	Yes	Yes	T5,T7,T50	Yes	T5,T7,T50	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T7,T50,T51	Yes	T7,T50,T51	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T7,T50	Yes	T5,T7,T50	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T7,T50	Yes	T5,T7,T50	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T55,*T260,*T261	Yes	T55,T260,T261	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T7,*T50	Yes	T5,T7,T50	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T7,T50	Yes	T5,T7,T50	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T203,T57,T83	Yes	T203,T57,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T790,T85	Yes	T83,T85,T170	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T85,T170	Yes	T83,T790,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T203,T57,T83	Yes	T203,T57,T83	OUTPUT
cio_rx_i	Yes	Yes	T1,T6,T35	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T7,T50,T51	Yes	T7,T50,T51	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T223,T224,T316	Yes	T223,T224,T316	OUTPUT
intr_tx_empty_o	Yes	Yes	T223,T224,T316	Yes	T223,T224,T316	OUTPUT
intr_rx_watermark_o	Yes	Yes	T223,T224,T316	Yes	T223,T224,T316	OUTPUT
intr_tx_done_o	Yes	Yes	T5,T223,T224	Yes	T5,T223,T224	OUTPUT
intr_rx_overflow_o	Yes	Yes	T5,T223,T224	Yes	T5,T223,T224	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T6,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T12,T127,T221	Yes	T12,T127,T221	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T12,T127,T221	Yes	T12,T127,T221	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T70,*T71	Yes	T55,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T82,T56	Yes	T73,T82,T56	INPUT
tl_i.a_valid	Yes	Yes	T57,T12,T58	Yes	T57,T12,T58	INPUT
tl_o.a_ready	Yes	Yes	T57,T12,T58	Yes	T57,T12,T58	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T137	Yes	T79,T80,T137	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T12,T127,T221	Yes	T12,T127,T221	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T12,T127,T221	Yes	T57,T12,T58	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T12,T127,T221	Yes	T57,T12,T58	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T137	Yes	T79,T80,T137	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T80,*T137	Yes	T79,T80,T137	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T137	Yes	T79,T80,T137	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T12,*T127,*T221	Yes	T12,T127,T221	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T12,T58	Yes	T57,T12,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T337,T83	Yes	T57,T337,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T337,T83	Yes	T57,T337,T83	OUTPUT
cio_rx_i	Yes	Yes	T127,T221,T345	Yes	T127,T221,T345	INPUT
cio_tx_o	Yes	Yes	T127,T221,T345	Yes	T127,T221,T345	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T127,T221,T345	Yes	T127,T221,T345	OUTPUT
intr_tx_empty_o	Yes	Yes	T127,T221,T345	Yes	T127,T221,T345	OUTPUT
intr_rx_watermark_o	Yes	Yes	T127,T221,T345	Yes	T127,T221,T345	OUTPUT
intr_tx_done_o	Yes	Yes	T127,T221,T345	Yes	T127,T221,T345	OUTPUT
intr_rx_overflow_o	Yes	Yes	T127,T221,T345	Yes	T127,T221,T345	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T6,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T70,*T71	Yes	T55,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T82,T56	Yes	T73,T82,T56	INPUT
tl_i.a_valid	Yes	Yes	T4,T160,T57	Yes	T4,T160,T57	INPUT
tl_o.a_ready	Yes	Yes	T4,T160,T57	Yes	T4,T160,T57	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T160,T161	Yes	T4,T160,T57	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T160,T161	Yes	T4,T160,T57	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T160,*T161	Yes	T4,T160,T161	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T160,T57	Yes	T4,T160,T57	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T791,T83	Yes	T57,T791,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T85,T170	Yes	T83,T85,T170	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T85,T170	Yes	T83,T85,T170	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T791,T83	Yes	T57,T791,T83	OUTPUT
cio_rx_i	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	INPUT
cio_tx_o	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
intr_tx_empty_o	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
intr_rx_watermark_o	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
intr_tx_done_o	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
intr_rx_overflow_o	Yes	Yes	T4,T160,T161	Yes	T4,T160,T161	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T6,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T15,T16,T12	Yes	T15,T16,T12	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T15,T16,T12	Yes	T15,T16,T12	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T70,*T71	Yes	T55,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T73,T82,T56	Yes	T73,T82,T56	INPUT
tl_i.a_valid	Yes	Yes	T57,T15,T16	Yes	T57,T15,T16	INPUT
tl_o.a_ready	Yes	Yes	T57,T15,T16	Yes	T57,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T137	Yes	T79,T80,T137	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T15,T16,T12	Yes	T15,T16,T12	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T15,T16,T12	Yes	T57,T15,T16	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T15,T16,T12	Yes	T57,T15,T16	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T137	Yes	T79,T80,T137	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T79,*T80,*T137	Yes	T79,T80,T137	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T137	Yes	T79,T80,T137	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T15,*T16,*T12	Yes	T15,T16,T12	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T15,T16	Yes	T57,T15,T16	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T57,T83,T58	Yes	T57,T83,T58	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T57,T83,T58	Yes	T57,T83,T58	OUTPUT
cio_rx_i	Yes	Yes	T15,T16,T210	Yes	T15,T16,T210	INPUT
cio_tx_o	Yes	Yes	T15,T16,T210	Yes	T15,T16,T210	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T15,T16,T210	Yes	T15,T16,T210	OUTPUT
intr_tx_empty_o	Yes	Yes	T15,T16,T210	Yes	T15,T16,T210	OUTPUT
intr_rx_watermark_o	Yes	Yes	T15,T16,T210	Yes	T15,T16,T210	OUTPUT
intr_tx_done_o	Yes	Yes	T15,T16,T210	Yes	T15,T16,T210	OUTPUT
intr_rx_overflow_o	Yes	Yes	T15,T16,T210	Yes	T15,T16,T210	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T99,T333	Yes	T316,T99,T333	OUTPUT

*Tests covering at least one bit in the range