Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
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Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_chip_env_0.1/chip_env_cov.sv

65 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
aes_fatal_fault 100.00 1 100 1 64 64
aes_recov_ctrl_update_err 100.00 1 100 1 64 64
aon_timer_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_recov_fault 100.00 1 100 1 64 64
csrng_fatal_alert 100.00 1 100 1 64 64
csrng_recov_alert 100.00 1 100 1 64 64
edn0_fatal_alert 100.00 1 100 1 64 64
edn0_recov_alert 100.00 1 100 1 64 64
edn1_fatal_alert 100.00 1 100 1 64 64
edn1_recov_alert 100.00 1 100 1 64 64
entropy_src_fatal_alert 100.00 1 100 1 64 64
entropy_src_recov_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_err 100.00 1 100 1 64 64
flash_ctrl_fatal_prim_flash_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_std_err 100.00 1 100 1 64 64
flash_ctrl_recov_err 100.00 1 100 1 64 64
flash_ctrl_recov_prim_flash_alert 100.00 1 100 1 64 64
gpio_fatal_fault 100.00 1 100 1 64 64
hmac_fatal_fault 100.00 1 100 1 64 64
i2c0_fatal_fault 100.00 1 100 1 64 64
i2c1_fatal_fault 100.00 1 100 1 64 64
i2c2_fatal_fault 100.00 1 100 1 64 64
keymgr_fatal_fault_err 100.00 1 100 1 64 64
keymgr_recov_operation_err 100.00 1 100 1 64 64
kmac_fatal_fault_err 100.00 1 100 1 64 64
kmac_recov_operation_err 100.00 1 100 1 64 64
lc_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
lc_ctrl_fatal_prog_error 100.00 1 100 1 64 64
lc_ctrl_fatal_state_error 100.00 1 100 1 64 64
otbn_fatal 100.00 1 100 1 64 64
otbn_recov 100.00 1 100 1 64 64
otp_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
otp_ctrl_fatal_check_error 100.00 1 100 1 64 64
otp_ctrl_fatal_macro_error 100.00 1 100 1 64 64
otp_ctrl_fatal_prim_otp_alert 100.00 1 100 1 64 64
otp_ctrl_recov_prim_otp_alert 100.00 1 100 1 64 64
pattgen_fatal_fault 100.00 1 100 1 64 64
pinmux_aon_fatal_fault 100.00 1 100 1 64 64
pwm_aon_fatal_fault 100.00 1 100 1 64 64
pwrmgr_aon_fatal_fault 100.00 1 100 1 64 64
rom_ctrl_fatal 100.00 1 100 1 64 64
rstmgr_aon_fatal_cnsty_fault 100.00 1 100 1 64 64
rstmgr_aon_fatal_fault 100.00 1 100 1 64 64
rv_core_ibex_fatal_hw_err 100.00 1 100 1 64 64
rv_core_ibex_fatal_sw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_hw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_sw_err 100.00 1 100 1 64 64
rv_dm_fatal_fault 100.00 1 100 1 64 64
rv_plic_fatal_fault 100.00 1 100 1 64 64
rv_timer_fatal_fault 100.00 1 100 1 64 64
sensor_ctrl_aon_fatal_alert 100.00 1 100 1 64 64
sensor_ctrl_aon_recov_alert 100.00 1 100 1 64 64
spi_device_fatal_fault 100.00 1 100 1 64 64
spi_host0_fatal_fault 100.00 1 100 1 64 64
spi_host1_fatal_fault 100.00 1 100 1 64 64
sram_ctrl_main_fatal_error 100.00 1 100 1 64 64
sram_ctrl_ret_aon_fatal_error 100.00 1 100 1 64 64
sysrst_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
uart0_fatal_fault 100.00 1 100 1 64 64
uart1_fatal_fault 100.00 1 100 1 64 64
uart2_fatal_fault 100.00 1 100 1 64 64
uart3_fatal_fault 100.00 1 100 1 64 64
usbdev_fatal_fault 100.00 1 100 1 64 64




Group Instance : adc_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance adc_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance adc_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_recov_ctrl_update_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_recov_ctrl_update_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_recov_ctrl_update_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aon_timer_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aon_timer_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aon_timer_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_recov_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_recov_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_recov_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_std_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_std_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_std_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : gpio_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance gpio_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance gpio_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : hmac_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance hmac_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance hmac_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_prog_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_prog_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_prog_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_state_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_state_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_state_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_recov
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_recov

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_recov
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_check_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_check_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_check_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_macro_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_macro_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_macro_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_recov_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_recov_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_recov_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pattgen_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pattgen_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pattgen_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pinmux_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pinmux_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pinmux_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwm_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwm_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwm_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwrmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwrmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwrmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rom_ctrl_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rom_ctrl_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_cnsty_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_cnsty_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_cnsty_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_dm_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_dm_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_dm_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_plic_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_plic_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_plic_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_timer_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_timer_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_device_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_device_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_main_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_main_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_main_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_ret_aon_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_ret_aon_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_ret_aon_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sysrst_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sysrst_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart3_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart3_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart3_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : usbdev_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance usbdev_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance usbdev_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4465 1 T232 818 T46 1 T443 495


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 127819 1 T1 1197 T61 587 T62 587


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 205 1 T46 1 T47 1 T81 52


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4232 1 T46 1 T47 1 T81 49


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2848 1 T46 1 T764 812 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 817 1 T46 1 T762 105 T763 102


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1940 1 T46 1 T47 1 T81 42


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 185 1 T295 1 T46 1 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4153 1 T46 1 T89 1091 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 199 1 T295 1 T46 1 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4117 1 T46 1 T724 1086 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 182 1 T46 1 T47 1 T81 44


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7765 1 T401 1128 T46 1 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 198 1 T46 1 T47 1 T81 36


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8560 1 T176 308 T177 364 T178 398


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3028 1 T5 1121 T46 1 T458 1729


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 172 1 T46 1 T47 1 T81 38


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 399 1 T103 2 T107 2 T176 10


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 177 1 T46 1 T47 1 T81 39


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1770 1 T46 1 T47 1 T81 42


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4728 1 T46 1 T795 1089 T796 1726


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7190 1 T393 524 T46 1 T360 814


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2857 1 T394 502 T46 1 T251 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3372 1 T62 812 T392 521 T723 505


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5969 1 T234 1732 T46 1 T781 1154


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 189 1 T46 1 T47 1 T81 53


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 125466 1 T1 1197 T61 587 T62 587


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 224 1 T46 1 T47 1 T81 61


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1761 1 T46 1 T322 502 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1909 1 T46 1 T47 1 T81 33


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8377 1 T46 1 T47 1 T793 811


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1400409 1 T1 1197 T6 106265 T61 587


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 217 1 T46 1 T400 1 T92 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2877 1 T164 524 T46 1 T251 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 58301 1 T1 567 T61 277 T62 278


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1023 1 T46 1 T47 1 T81 46


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5856 1 T165 809 T46 1 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 210 1 T46 1 T47 1 T81 51


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6060 1 T46 1 T223 519 T794 533


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4234 1 T46 1 T79 524 T84 817


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4004 1 T759 819 T359 816 T46 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 11060 1 T185 817 T231 812 T261 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4749 1 T424 1120 T46 1 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2628 1 T357 809 T46 1 T368 807


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2072 1 T46 1 T47 1 T81 38


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 26880 1 T3 247 T233 2851 T247 799


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4641 1 T46 1 T47 1 T81 47


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 142 1 T46 1 T47 1 T81 25


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 334 1 T1 1 T46 1 T251 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 9996 1 T318 1726 T307 1713 T797 1160


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2537 1 T46 1 T251 1 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2081 1 T46 1 T771 520 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5293 1 T46 1 T299 1 T134 164


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 43093 1 T18 1265 T133 669 T46 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1826 1 T46 1 T221 815 T47 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8997 1 T46 1 T425 1102 T251 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3661 1 T46 1 T798 1297 T799 1293


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 200 1 T46 1 T47 1 T81 50


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 217 1 T46 1 T47 1 T81 39


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3185 1 T46 1 T788 809 T789 821


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1851 1 T46 1 T251 2 T384 812


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2871 1 T46 1 T251 1 T769 816


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7579 1 T367 818 T768 504 T770 505


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1569 1 T61 812 T46 1 T251 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8760 1 T406 860 T46 1 T800 1311

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%