Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3898382	1			T71	1112		T72	106		T73	69
values[2]	785500	1			T71	327		T72	45		T73	30
values[3]	113570	1			T71	9		T73	1		T77	2
values[4]	61214	1			T131	117		T440	1		T429	536
values[5]	40337	1			T131	79		T429	396		T883	2
values[6]	29894	1			T131	50		T429	289		T883	2
values[7]	24403	1			T131	44		T429	213		T883	2
values[8]	21079	1			T131	38		T429	160		T883	2
values[9]	18268	1			T131	37		T429	90		T883	2
values[10]	16852	1			T131	43		T429	84		T883	2
values[11]	15510	1			T131	46		T429	66		T883	2
values[12]	14870	1			T131	47		T429	50		T883	2
values[13]	14044	1			T131	31		T429	53		T883	2
values[14]	13639	1			T131	10		T429	30		T883	2
values[15]	12865	1			T131	13		T429	25		T883	3
values[16]	12551	1			T131	14		T429	22		T883	2
values[17]	12274	1			T131	8		T429	11		T883	2
values[18]	11776	1			T131	10		T429	25		T883	2
values[19]	11593	1			T131	6		T429	33		T883	2
values[20]	11536	1			T131	7		T429	18		T883	2
values[21]	11246	1			T131	7		T429	13		T883	2
values[22]	10492	1			T131	9		T429	8		T883	2
values[23]	10118	1			T131	6		T429	14		T883	2
values[24]	9969	1			T131	6		T429	11		T883	2
values[25]	9253	1			T131	14		T429	9		T883	2
values[26]	8808	1			T131	13		T429	7		T883	2
values[27]	8661	1			T131	15		T429	6		T883	2
values[28]	8358	1			T131	28		T429	4		T883	2
values[29]	7734	1			T131	12		T429	7		T883	2
values[30]	7108	1			T131	8		T429	5		T883	2
values[31]	6521	1			T131	6		T429	10		T883	2
values[32]	6139	1			T131	3		T429	17		T883	2
values[33]	5950	1			T131	2		T429	5		T883	2
values[34]	5472	1			T131	4		T429	5		T883	2
values[35]	4996	1			T131	6		T429	3		T883	2
values[36]	4813	1			T131	6		T429	3		T883	2
values[37]	4623	1			T131	4		T429	3		T883	2
values[38]	4284	1			T131	3		T429	2		T883	2
values[39]	4054	1			T131	4		T429	5		T883	2
values[40]	3996	1			T131	8		T429	3		T883	2
values[41]	3970	1			T131	8		T429	3		T883	2
values[42]	3710	1			T131	5		T429	4		T883	2
values[43]	3541	1			T131	6		T429	3		T883	2
values[44]	3435	1			T131	6		T429	8		T883	2
values[45]	3404	1			T131	2		T429	9		T883	2
values[46]	3331	1			T131	4		T429	10		T883	2
values[47]	3335	1			T131	7		T429	3		T883	2
values[48]	3324	1			T131	3		T429	6		T883	2
values[49]	3264	1			T131	2		T429	5		T883	3
values[50]	3081	1			T131	7		T429	5		T883	2
values[51]	2956	1			T131	2		T429	3		T883	2
values[52]	2974	1			T131	5		T429	4		T883	2
values[53]	2888	1			T131	4		T429	7		T883	2
values[54]	2741	1			T131	3		T429	12		T883	2
values[55]	2698	1			T131	4		T429	12		T883	2
values[56]	2669	1			T131	5		T429	9		T883	3
values[57]	2620	1			T131	2		T429	8		T883	2
values[58]	2600	1			T131	2		T429	4		T883	2
values[59]	2556	1			T131	2		T429	5		T883	2
values[60]	2618	1			T131	4		T429	4		T883	2
values[61]	2913	1			T131	4		T429	3		T883	2
values[62]	4494	1			T131	2		T429	5		T883	2
values[63]	12342	1			T131	22		T429	43		T883	2
values[64]	234019	1			T131	126		T429	130		T883	434

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4988755	1			T71	1062		T72	140		T73	142
values[2]	843393	1			T71	318		T72	36		T73	36
values[3]	85546	1			T71	57		T73	5		T77	23
values[4]	14908	1			T71	5		T73	1		T77	1
values[5]	5670	1			T131	51		T883	1		T551	11
values[6]	3706	1			T131	48		T551	5		T552	21
values[7]	2898	1			T131	56		T551	1		T552	22
values[8]	2338	1			T131	28		T552	21		T553	2
values[9]	2015	1			T131	15		T552	23		T560	1
values[10]	1774	1			T131	5		T552	26		T560	1
values[11]	1694	1			T131	8		T552	41		T560	1
values[12]	1512	1			T131	6		T552	35		T560	1
values[13]	1439	1			T131	7		T552	19		T560	1
values[14]	1392	1			T131	8		T552	11		T560	1
values[15]	1290	1			T131	7		T552	11		T560	1
values[16]	1280	1			T131	9		T552	4		T560	1
values[17]	1059	1			T131	3		T552	3		T560	1
values[18]	999	1			T131	4		T552	5		T560	1
values[19]	963	1			T131	5		T552	10		T560	1
values[20]	947	1			T131	5		T552	13		T560	1
values[21]	942	1			T131	4		T552	15		T560	1
values[22]	901	1			T131	1		T552	11		T560	1
values[23]	901	1			T131	6		T552	6		T560	1
values[24]	804	1			T131	7		T552	4		T560	1
values[25]	749	1			T131	11		T552	7		T560	1
values[26]	764	1			T131	6		T552	14		T560	1
values[27]	758	1			T131	7		T552	8		T560	1
values[28]	721	1			T131	3		T552	4		T560	1
values[29]	697	1			T131	3		T552	5		T560	1
values[30]	687	1			T131	3		T552	8		T560	1
values[31]	660	1			T131	6		T552	9		T560	1
values[32]	700	1			T131	7		T552	12		T560	1
values[33]	617	1			T131	3		T552	9		T560	1
values[34]	625	1			T131	1		T552	12		T560	1
values[35]	591	1			T131	3		T552	15		T560	1
values[36]	542	1			T131	1		T552	10		T560	1
values[37]	523	1			T131	1		T552	11		T560	1
values[38]	503	1			T131	4		T552	4		T560	1
values[39]	490	1			T131	3		T552	4		T560	1
values[40]	471	1			T131	1		T552	10		T560	1
values[41]	485	1			T552	9		T560	1		T880	4
values[42]	511	1			T552	19		T560	1		T880	5
values[43]	456	1			T552	9		T560	1		T880	2
values[44]	452	1			T552	3		T560	1		T880	3
values[45]	475	1			T552	3		T560	1		T880	1
values[46]	443	1			T552	3		T560	1		T880	3
values[47]	420	1			T552	4		T560	1		T880	3
values[48]	406	1			T552	9		T560	1		T880	1
values[49]	402	1			T552	2		T560	1		T880	1
values[50]	415	1			T552	1		T560	1		T880	3
values[51]	412	1			T552	1		T560	1		T880	2
values[52]	408	1			T552	2		T560	1		T880	1
values[53]	409	1			T552	1		T560	1		T880	1
values[54]	406	1			T552	1		T560	1		T880	1
values[55]	409	1			T552	1		T560	1		T880	1
values[56]	389	1			T552	1		T560	1		T880	1
values[57]	399	1			T552	1		T560	1		T880	2
values[58]	393	1			T552	2		T560	1		T880	2
values[59]	379	1			T552	2		T560	1		T880	1
values[60]	372	1			T552	2		T560	1		T880	1
values[61]	439	1			T552	5		T560	1		T880	1
values[62]	645	1			T552	7		T560	1		T880	3
values[63]	2565	1			T552	30		T560	1		T880	30
values[64]	28805	1			T552	87		T560	202		T880	91

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	594859	1			T71	11		T72	1		T73	1
values[2]	2787639	1			T71	490		T72	96		T73	20
values[3]	1216676	1			T71	867		T72	53		T73	100
values[4]	154226	1			T71	11		T72	1		T73	1
values[5]	79663	1			T131	314		T440	13		T564	1
values[6]	52666	1			T131	149		T440	17		T429	384
values[7]	38714	1			T131	108		T440	14		T429	307
values[8]	31188	1			T131	81		T440	3		T429	275
values[9]	26273	1			T131	54		T440	4		T429	242
values[10]	23067	1			T131	38		T440	2		T429	164
values[11]	21133	1			T131	38		T429	157		T883	2
values[12]	19709	1			T131	63		T429	142		T883	2
values[13]	17978	1			T131	33		T429	90		T883	2
values[14]	16859	1			T131	31		T429	74		T883	2
values[15]	16169	1			T131	18		T429	76		T883	2
values[16]	15239	1			T131	30		T429	36		T883	2
values[17]	14411	1			T131	19		T429	17		T883	2
values[18]	13987	1			T131	29		T429	26		T883	2
values[19]	13414	1			T131	30		T429	23		T883	2
values[20]	12882	1			T131	32		T429	19		T883	2
values[21]	12283	1			T131	14		T429	21		T883	2
values[22]	11960	1			T131	13		T429	24		T883	2
values[23]	11474	1			T131	13		T429	21		T883	2
values[24]	11184	1			T131	12		T429	23		T883	2
values[25]	10734	1			T131	7		T429	19		T883	2
values[26]	10440	1			T131	13		T429	17		T883	2
values[27]	9965	1			T131	8		T429	14		T883	2
values[28]	9319	1			T131	8		T429	11		T883	2
values[29]	8792	1			T131	6		T429	6		T883	2
values[30]	8034	1			T131	7		T429	9		T883	3
values[31]	7475	1			T131	10		T429	9		T883	2
values[32]	6787	1			T131	8		T429	7		T883	2
values[33]	6138	1			T131	12		T429	6		T883	2
values[34]	5759	1			T131	7		T429	5		T883	2
values[35]	5419	1			T131	10		T429	8		T883	2
values[36]	4868	1			T131	5		T429	3		T883	2
values[37]	4670	1			T131	5		T429	7		T883	2
values[38]	4605	1			T131	7		T429	3		T883	2
values[39]	4473	1			T131	12		T429	3		T883	2
values[40]	4215	1			T131	10		T429	8		T883	2
values[41]	3947	1			T131	7		T429	14		T883	2
values[42]	3874	1			T131	10		T429	12		T883	2
values[43]	3803	1			T131	12		T429	4		T883	2
values[44]	3656	1			T131	24		T429	6		T883	2
values[45]	3726	1			T131	11		T429	7		T883	2
values[46]	3687	1			T131	11		T429	7		T883	2
values[47]	3618	1			T131	20		T429	7		T883	2
values[48]	3497	1			T131	14		T429	6		T883	2
values[49]	3448	1			T131	14		T429	9		T883	2
values[50]	3473	1			T131	25		T429	11		T883	2
values[51]	3395	1			T131	28		T429	13		T883	2
values[52]	3219	1			T131	28		T429	8		T883	2
values[53]	3184	1			T131	19		T429	4		T883	2
values[54]	3064	1			T131	7		T429	2		T883	2
values[55]	3030	1			T131	7		T429	3		T883	2
values[56]	3071	1			T131	7		T429	3		T883	2
values[57]	3034	1			T131	9		T429	6		T883	2
values[58]	2980	1			T131	10		T429	16		T883	2
values[59]	2928	1			T131	13		T429	8		T883	2
values[60]	2892	1			T131	12		T429	5		T883	2
values[61]	2945	1			T131	22		T429	6		T883	3
values[62]	3936	1			T131	18		T429	24		T883	2
values[63]	9713	1			T131	12		T429	50		T883	2
values[64]	227076	1			T131	56		T429	73		T883	403