Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2049892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38732065

1

T1

10538

T2

17285

T3

14426

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28438537	1			T1	4199		T2	13180		T3	6383
values[0x0]	10864680	1			T1	6339		T2	4105		T3	8043
values[0x1]	1478740	1			T1	724		T2	3743		T3	762

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	718824	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40063133

1

T1

11262

T2

21028

T3

15188

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19092158	1			T1	5632		T2	10514		T3	7595
valid_sources[0x01]	19088304	1			T1	5630		T2	10514		T3	7593
valid_sources[0x02]	43144	1			T213	1		T150	169		T151	185
valid_sources[0x03]	41197	1			T150	158		T151	178		T390	174
valid_sources[0x04]	41865	1			T150	169		T151	251		T390	208
valid_sources[0x05]	41904	1			T52	1		T212	1		T213	1
valid_sources[0x06]	42246	1			T75	2		T52	1		T150	169
valid_sources[0x07]	41842	1			T150	170		T151	220		T390	151
valid_sources[0x08]	42340	1			T150	157		T151	178		T390	143
valid_sources[0x09]	42032	1			T213	1		T150	169		T151	194
valid_sources[0x0a]	42257	1			T75	4		T52	2		T212	2
valid_sources[0x0b]	42083	1			T150	154		T151	184		T390	139
valid_sources[0x0c]	41692	1			T52	1		T150	180		T151	203
valid_sources[0x0d]	41852	1			T52	3		T150	168		T151	186
valid_sources[0x0e]	41391	1			T150	186		T151	111		T390	172
valid_sources[0x0f]	41426	1			T52	1		T213	4		T150	169
valid_sources[0x10]	41753	1			T212	2		T150	185		T151	118
valid_sources[0x11]	41705	1			T212	4		T150	164		T151	53
valid_sources[0x12]	41627	1			T52	1		T213	2		T150	164
valid_sources[0x13]	41378	1			T213	2		T150	172		T151	153
valid_sources[0x14]	41607	1			T75	3		T213	6		T150	166
valid_sources[0x15]	42119	1			T52	1		T76	39		T213	1
valid_sources[0x16]	42043	1			T150	167		T151	250		T390	222
valid_sources[0x17]	41767	1			T52	1		T212	2		T150	146
valid_sources[0x18]	42135	1			T75	1		T213	1		T150	167
valid_sources[0x19]	41654	1			T212	2		T213	1		T150	134
valid_sources[0x1a]	41664	1			T212	9		T150	153		T151	236
valid_sources[0x1b]	41995	1			T75	2		T52	1		T150	170
valid_sources[0x1c]	41687	1			T150	179		T151	158		T390	123
valid_sources[0x1d]	41247	1			T75	1		T52	1		T213	1
valid_sources[0x1e]	41969	1			T213	3		T150	183		T151	190
valid_sources[0x1f]	41265	1			T52	1		T150	145		T151	246
valid_sources[0x20]	42062	1			T150	161		T151	151		T390	79

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27644401

1

T1

4199

T2

13180

T3

6383

values[0x0]

all_enables

biggest_size

10803014

1

T1

6339

T2

4105

T3

8043

values[0x1]

all_enables

biggest_size

284650

1

T75

20

T52

17

T76

13

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2943919	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

465744

1

T71

3

T72

16

T73

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1155617	1			T71	31		T72	50		T73	36
values[0x0]	1098507	1			T71	4		T72	45		T73	31
values[0x1]	1155539	1			T71	22		T72	56		T73	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2278838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1130825

1

T71

19

T72

40

T73

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52538	1			T73	2		T131	347		T555	1
valid_sources[0x01]	51833	1			T71	2		T72	1		T131	207
valid_sources[0x02]	53739	1			T71	2		T73	3		T131	272
valid_sources[0x03]	53876	1			T71	2		T77	1		T131	321
valid_sources[0x04]	54395	1			T73	1		T131	201		T465	3
valid_sources[0x05]	52983	1			T71	2		T72	2		T73	2
valid_sources[0x06]	52416	1			T131	103		T440	81		T464	1
valid_sources[0x07]	54507	1			T77	1		T131	248		T555	1
valid_sources[0x08]	52460	1			T71	1		T73	2		T131	191
valid_sources[0x09]	53673	1			T77	1		T131	155		T555	9
valid_sources[0x0a]	52376	1			T71	1		T72	10		T131	131
valid_sources[0x0b]	54045	1			T71	1		T73	4		T131	186
valid_sources[0x0c]	53735	1			T72	1		T73	1		T77	1
valid_sources[0x0d]	53483	1			T72	3		T73	7		T131	271
valid_sources[0x0e]	53561	1			T71	2		T131	226		T440	59
valid_sources[0x0f]	53251	1			T71	1		T131	188		T440	35
valid_sources[0x10]	53039	1			T71	2		T73	2		T131	214
valid_sources[0x11]	53561	1			T73	2		T77	1		T131	196
valid_sources[0x12]	53717	1			T73	3		T77	1		T131	190
valid_sources[0x13]	52444	1			T71	1		T131	338		T440	38
valid_sources[0x14]	53333	1			T72	3		T73	1		T131	219
valid_sources[0x15]	53997	1			T71	2		T73	1		T131	185
valid_sources[0x16]	52694	1			T72	16		T73	1		T131	440
valid_sources[0x17]	53602	1			T71	1		T73	4		T131	242
valid_sources[0x18]	53033	1			T73	3		T131	265		T440	53
valid_sources[0x19]	53966	1			T71	3		T73	1		T131	164
valid_sources[0x1a]	51794	1			T71	2		T72	9		T73	4
valid_sources[0x1b]	53272	1			T71	1		T77	1		T131	199
valid_sources[0x1c]	53747	1			T72	3		T77	1		T131	255
valid_sources[0x1d]	53336	1			T73	2		T77	1		T131	299
valid_sources[0x1e]	52622	1			T71	1		T72	5		T77	1
valid_sources[0x1f]	52836	1			T71	1		T131	277		T555	8
valid_sources[0x20]	53654	1			T72	6		T73	4		T131	309

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49260

1

T71

2

T72

2

T73

2

values[0x0]

all_enables

biggest_size

367232

1

T71

1

T72

11

T73

11

values[0x1]

all_enables

biggest_size

49252

1

T72

3

T73

3

T77

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3123763	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

509114

1

T71

8

T72

23

T73

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1243039	1			T71	28		T72	61		T73	58
values[0x0]	1144671	1			T71	4		T72	56		T73	64
values[0x1]	1245167	1			T71	28		T72	59		T73	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2397977	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1234900

1

T71

26

T72

51

T73

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55969	1			T71	1		T72	13		T73	21
valid_sources[0x01]	55583	1			T72	3		T73	11		T77	2
valid_sources[0x02]	56766	1			T77	1		T131	279		T555	11
valid_sources[0x03]	58381	1			T71	1		T77	2		T131	329
valid_sources[0x04]	57429	1			T72	3		T131	308		T555	5
valid_sources[0x05]	56457	1			T71	1		T73	4		T131	168
valid_sources[0x06]	56476	1			T71	2		T72	2		T77	1
valid_sources[0x07]	56626	1			T71	2		T73	2		T77	2
valid_sources[0x08]	56085	1			T72	6		T73	6		T77	1
valid_sources[0x09]	56776	1			T71	2		T72	1		T131	197
valid_sources[0x0a]	56569	1			T73	7		T77	1		T131	228
valid_sources[0x0b]	57026	1			T71	2		T73	2		T131	172
valid_sources[0x0c]	56985	1			T71	1		T72	3		T73	1
valid_sources[0x0d]	57309	1			T131	199		T555	34		T440	53
valid_sources[0x0e]	56608	1			T71	3		T72	6		T73	2
valid_sources[0x0f]	57457	1			T71	1		T73	1		T131	162
valid_sources[0x10]	56803	1			T71	2		T73	7		T77	1
valid_sources[0x11]	56897	1			T71	1		T72	1		T73	12
valid_sources[0x12]	56227	1			T72	6		T77	1		T131	229
valid_sources[0x13]	56136	1			T73	1		T77	1		T131	292
valid_sources[0x14]	56991	1			T73	3		T131	182		T440	70
valid_sources[0x15]	56535	1			T131	210		T555	2		T440	66
valid_sources[0x16]	56644	1			T72	3		T131	235		T440	82
valid_sources[0x17]	58305	1			T71	1		T72	6		T77	1
valid_sources[0x18]	57062	1			T71	2		T73	3		T131	238
valid_sources[0x19]	57333	1			T131	232		T440	65		T429	323
valid_sources[0x1a]	56359	1			T73	1		T131	295		T555	3
valid_sources[0x1b]	57146	1			T71	1		T131	194		T440	63
valid_sources[0x1c]	57198	1			T72	5		T73	13		T131	317
valid_sources[0x1d]	57175	1			T71	1		T73	5		T77	1
valid_sources[0x1e]	57020	1			T71	2		T72	5		T77	1
valid_sources[0x1f]	56023	1			T72	5		T77	1		T131	220
valid_sources[0x20]	56142	1			T71	2		T72	4		T131	219

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53648

1

T71

2

T72

2

T73

1

values[0x0]

all_enables

biggest_size

402113

1

T71

3

T72

18

T73

23

values[0x1]

all_enables

biggest_size

53353

1

T71

3

T72

3

T73

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2963200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469585

1

T71

5

T72

24

T73

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1162847	1			T71	33		T72	50		T73	49
values[0x0]	1106640	1			T71	3		T72	52		T73	32
values[0x1]	1163298	1			T71	22		T72	49		T73	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2294036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1138749

1

T71

18

T72

52

T73

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53376	1			T131	244		T555	6		T440	43
valid_sources[0x01]	53894	1			T71	2		T77	1		T131	303
valid_sources[0x02]	53215	1			T71	2		T73	1		T131	267
valid_sources[0x03]	53696	1			T73	1		T131	284		T555	2
valid_sources[0x04]	53504	1			T71	2		T72	3		T73	2
valid_sources[0x05]	53494	1			T72	8		T73	2		T131	239
valid_sources[0x06]	52285	1			T71	1		T73	1		T131	236
valid_sources[0x07]	54389	1			T71	1		T73	2		T131	199
valid_sources[0x08]	53281	1			T131	260		T440	43		T464	3
valid_sources[0x09]	53723	1			T71	2		T72	8		T73	3
valid_sources[0x0a]	53524	1			T71	1		T73	1		T131	277
valid_sources[0x0b]	53389	1			T71	1		T73	2		T131	237
valid_sources[0x0c]	53908	1			T73	1		T131	193		T555	2
valid_sources[0x0d]	53589	1			T73	4		T131	225		T555	1
valid_sources[0x0e]	54184	1			T73	4		T131	288		T555	3
valid_sources[0x0f]	54160	1			T73	1		T77	1		T131	245
valid_sources[0x10]	53329	1			T71	1		T131	287		T555	3
valid_sources[0x11]	54088	1			T71	1		T131	230		T555	1
valid_sources[0x12]	53128	1			T71	1		T72	2		T73	2
valid_sources[0x13]	53277	1			T71	3		T72	15		T73	2
valid_sources[0x14]	54148	1			T71	1		T73	1		T131	277
valid_sources[0x15]	54090	1			T71	1		T72	3		T73	3
valid_sources[0x16]	53925	1			T72	5		T73	1		T131	233
valid_sources[0x17]	53608	1			T71	2		T73	4		T77	1
valid_sources[0x18]	53353	1			T71	1		T72	1		T131	207
valid_sources[0x19]	53127	1			T71	1		T73	2		T131	284
valid_sources[0x1a]	53124	1			T73	1		T131	240		T440	42
valid_sources[0x1b]	53551	1			T71	1		T72	9		T73	1
valid_sources[0x1c]	53039	1			T71	1		T73	2		T77	1
valid_sources[0x1d]	53722	1			T73	3		T131	293		T465	1
valid_sources[0x1e]	53784	1			T71	1		T72	2		T73	2
valid_sources[0x1f]	53968	1			T71	1		T73	1		T131	237
valid_sources[0x20]	53369	1			T72	1		T73	3		T77	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49341

1

T71

1

T72

3

T73

2

values[0x0]

all_enables

biggest_size

370732

1

T72

17

T73

9

T131

1760

values[0x1]

all_enables

biggest_size

49512

1

T71

4

T72

4

T73

2