Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533448982	61573244	0	0
DepthKnown_A	533448982	533340715	0	0
RvalidKnown_A	533448982	533340715	0	0
WreadyKnown_A	533448982	533340715	0	0
gen_passthru_fifo.paramCheckPass	1033	1033	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	61573244	0	0
T1	270948	19202	0	0
T2	223751	22897	0	0
T3	216129	25800	0	0
T4	121617	147383	0	0
T5	160576	22133	0	0
T6	412737	163674	0	0
T43	128880	143786	0	0
T45	185105	24048	0	0
T61	226022	29683	0	0
T83	144498	18105	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533448982	47674742	0	0
DepthKnown_A	533448982	533340715	0	0
RvalidKnown_A	533448982	533340715	0	0
WreadyKnown_A	533448982	533340715	0	0
gen_passthru_fifo.paramCheckPass	1033	1033	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	47674742	0	0
T1	270948	15225	0	0
T2	223751	18924	0	0
T3	216129	19996	0	0
T4	121617	115981	0	0
T5	160576	16839	0	0
T6	412737	82205	0	0
T43	128880	124358	0	0
T45	185105	21410	0	0
T61	226022	20103	0	0
T83	144498	15571	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533448982	45233117	0	0
DepthKnown_A	533448982	533340715	0	0
RvalidKnown_A	533448982	533340715	0	0
WreadyKnown_A	533448982	533340715	0	0
gen_passthru_fifo.paramCheckPass	1033	1033	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	45233117	0	0
T1	270948	11515	0	0
T2	223751	21231	0	0
T3	216129	15567	0	0
T4	121617	92617	0	0
T5	160576	9946	0	0
T6	412737	13167	0	0
T43	128880	175811	0	0
T45	185105	4466	0	0
T61	226022	14250	0	0
T83	144498	5385	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533448982	38191918	0	0
DepthKnown_A	533448982	533340715	0	0
RvalidKnown_A	533448982	533340715	0	0
WreadyKnown_A	533448982	533340715	0	0
gen_passthru_fifo.paramCheckPass	1033	1033	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	38191918	0	0
T1	270948	11262	0	0
T2	223751	21028	0	0
T3	216129	15188	0	0
T4	121617	91013	0	0
T5	160576	9662	0	0
T6	412737	12186	0	0
T43	128880	116816	0	0
T45	185105	4262	0	0
T61	226022	13861	0	0
T83	144498	5207	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533448982	533340715	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1033	1033	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	622051232	94075	0	0
DepthKnown_A	622051232	621927076	0	0
RvalidKnown_A	622051232	621927076	0	0
WreadyKnown_A	622051232	621927076	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	94075	0	0
T1	270948	29	0	0
T2	223751	53	0	0
T3	216129	104	0	0
T4	121617	209	0	0
T5	160576	26	0	0
T6	412737	73	0	0
T43	128880	34	0	0
T45	185105	78	0	0
T61	226022	151	0	0
T83	144498	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	622051232	95858	0	0
DepthKnown_A	622051232	621927076	0	0
RvalidKnown_A	622051232	621927076	0	0
WreadyKnown_A	622051232	621927076	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	95858	0	0
T1	270948	29	0	0
T2	223751	53	0	0
T3	216129	104	0	0
T4	121617	209	0	0
T5	160576	26	0	0
T6	412737	73	0	0
T43	128880	34	0	0
T45	185105	78	0	0
T61	226022	151	0	0
T83	144498	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	622051232	53318	0	0
DepthKnown_A	622051232	621927076	0	0
RvalidKnown_A	622051232	621927076	0	0
WreadyKnown_A	622051232	621927076	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	53318	0	0
T1	270948	25	0	0
T2	223751	52	0	0
T3	216129	98	0	0
T4	121617	198	0	0
T5	160576	23	0	0
T6	412737	69	0	0
T43	128880	5	0	0
T45	185105	77	0	0
T61	226022	95	0	0
T83	144498	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	622051232	53318	0	0
DepthKnown_A	622051232	621927076	0	0
RvalidKnown_A	622051232	621927076	0	0
WreadyKnown_A	622051232	621927076	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	53318	0	0
T1	270948	25	0	0
T2	223751	52	0	0
T3	216129	98	0	0
T4	121617	198	0	0
T5	160576	23	0	0
T6	412737	69	0	0
T43	128880	5	0	0
T45	185105	77	0	0
T61	226022	95	0	0
T83	144498	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	622051232	40757	0	0
DepthKnown_A	622051232	621927076	0	0
RvalidKnown_A	622051232	621927076	0	0
WreadyKnown_A	622051232	621927076	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	40757	0	0
T1	270948	4	0	0
T2	223751	1	0	0
T3	216129	6	0	0
T4	121617	11	0	0
T5	160576	3	0	0
T6	412737	4	0	0
T43	128880	29	0	0
T45	185105	1	0	0
T61	226022	56	0	0
T83	144498	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	622051232	42540	0	0
DepthKnown_A	622051232	621927076	0	0
RvalidKnown_A	622051232	621927076	0	0
WreadyKnown_A	622051232	621927076	0	0
gen_passthru_fifo.paramCheckPass	2943	2943	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	42540	0	0
T1	270948	4	0	0
T2	223751	1	0	0
T3	216129	6	0	0
T4	121617	11	0	0
T5	160576	3	0	0
T6	412737	4	0	0
T43	128880	29	0	0
T45	185105	1	0	0
T61	226022	56	0	0
T83	144498	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622051232	621927076	0	0
T1	270948	270839	0	0
T2	223751	223689	0	0
T3	216129	216009	0	0
T4	121617	121556	0	0
T5	160576	160525	0	0
T6	412737	412709	0	0
T43	128880	128874	0	0
T45	185105	185050	0	0
T61	226022	225902	0	0
T83	144498	144443	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943	2943	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T43	1	1	0	0
T45	1	1	0	0
T61	1	1	0	0
T83	1	1	0	0