Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T43	Yes	T1,T2,T43	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T43	Yes	T1,T2,T43	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T43	Yes	T1,T2,T43	INPUT
tl_o.a_ready	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T263,*T76,*T71	Yes	T263,T76,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T43,*T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T61,T367,T768	Yes	T61,T367,T768	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T162,T80,T81	Yes	T162,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T162,T80,T81	Yes	T162,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T61,T367,T768	Yes	T61,T367,T768	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T2,T229,T152	Yes	T2,T229,T152	OUTPUT
intr_tx_empty_o	Yes	Yes	T2,T229,T152	Yes	T2,T229,T152	OUTPUT
intr_rx_watermark_o	Yes	Yes	T2,T229,T152	Yes	T2,T229,T152	OUTPUT
intr_tx_done_o	Yes	Yes	T2,T229,T106	Yes	T2,T229,T106	OUTPUT
intr_rx_overflow_o	Yes	Yes	T2,T229,T106	Yes	T2,T229,T106	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T43	Yes	T1,T2,T43	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T43	Yes	T1,T2,T43	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T43	Yes	T1,T2,T43	INPUT
tl_o.a_ready	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_error	Yes	Yes	T71,T73,T77	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T263,*T76,*T71	Yes	T263,T76,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T43,*T44	Yes	T2,T43,T44	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T46,T251,T162	Yes	T46,T251,T162	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T162,T80,T81	Yes	T162,T80,T81	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T162,T80,T81	Yes	T162,T80,T81	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T46,T251,T162	Yes	T46,T251,T162	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T2,T229,T122	Yes	T2,T229,T122	OUTPUT
intr_tx_empty_o	Yes	Yes	T2,T229,T122	Yes	T2,T229,T122	OUTPUT
intr_rx_watermark_o	Yes	Yes	T2,T229,T122	Yes	T2,T229,T122	OUTPUT
intr_tx_done_o	Yes	Yes	T2,T229,T106	Yes	T2,T229,T106	OUTPUT
intr_rx_overflow_o	Yes	Yes	T2,T229,T106	Yes	T2,T229,T106	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T325,T339	Yes	T11,T325,T339	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T325,T339	Yes	T11,T325,T339	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	INPUT
tl_i.a_valid	Yes	Yes	T46,T11,T325	Yes	T46,T11,T325	INPUT
tl_o.a_ready	Yes	Yes	T46,T11,T325	Yes	T46,T11,T325	OUTPUT
tl_o.d_error	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T325,T339	Yes	T11,T325,T339	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T11,T325,T251	Yes	T46,T11,T325	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T11,T325,T251	Yes	T46,T11,T325	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T71,*T73	Yes	T76,T71,T73	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T325,*T339	Yes	T11,T325,T339	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T46,T11,T325	Yes	T46,T11,T325	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T46,T251,T769	Yes	T46,T251,T769	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T166	Yes	T80,T81,T166	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T166	Yes	T80,T81,T166	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T46,T251,T769	Yes	T46,T251,T769	OUTPUT
cio_rx_i	Yes	Yes	T31,T339,T340	Yes	T9,T31,T32	INPUT
cio_tx_o	Yes	Yes	T339,T340,T341	Yes	T339,T340,T341	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T325,T339,T340	Yes	T325,T339,T340	OUTPUT
intr_tx_empty_o	Yes	Yes	T325,T339,T340	Yes	T325,T339,T340	OUTPUT
intr_rx_watermark_o	Yes	Yes	T325,T339,T340	Yes	T325,T339,T340	OUTPUT
intr_tx_done_o	Yes	Yes	T325,T339,T340	Yes	T325,T339,T340	OUTPUT
intr_rx_overflow_o	Yes	Yes	T325,T339,T340	Yes	T325,T339,T340	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T152,T11,T325	Yes	T152,T11,T325	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T152,T11,T325	Yes	T152,T11,T325	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	INPUT
tl_i.a_valid	Yes	Yes	T152,T46,T11	Yes	T152,T46,T11	INPUT
tl_o.a_ready	Yes	Yes	T152,T46,T11	Yes	T152,T46,T11	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T77,T555	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T152,T11,T325	Yes	T152,T11,T325	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T152,T11,T325	Yes	T152,T46,T11	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T152,T11,T325	Yes	T152,T46,T11	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T71,*T77	Yes	T76,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T152,*T11,*T325	Yes	T152,T11,T325	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T152,T46,T11	Yes	T152,T46,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T367,T768,T770	Yes	T367,T768,T770	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T166	Yes	T80,T81,T166	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T166	Yes	T80,T81,T166	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T367,T768,T770	Yes	T367,T768,T770	OUTPUT
cio_rx_i	Yes	Yes	T152,T153,T336	Yes	T152,T153,T336	INPUT
cio_tx_o	Yes	Yes	T152,T153,T336	Yes	T152,T153,T336	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T152,T325,T153	Yes	T152,T325,T153	OUTPUT
intr_tx_empty_o	Yes	Yes	T152,T325,T153	Yes	T152,T325,T153	OUTPUT
intr_rx_watermark_o	Yes	Yes	T152,T325,T153	Yes	T152,T325,T153	OUTPUT
intr_tx_done_o	Yes	Yes	T152,T325,T153	Yes	T152,T325,T153	OUTPUT
intr_rx_overflow_o	Yes	Yes	T152,T325,T153	Yes	T152,T325,T153	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T11,T325	Yes	T14,T11,T325	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T11,T325	Yes	T14,T11,T325	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	INPUT
tl_i.a_valid	Yes	Yes	T14,T46,T11	Yes	T14,T46,T11	INPUT
tl_o.a_ready	Yes	Yes	T14,T46,T11	Yes	T14,T46,T11	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T11,T325	Yes	T14,T11,T325	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T11,T325	Yes	T14,T46,T11	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T11,T325	Yes	T14,T46,T11	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T71,*T72	Yes	T76,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T11,*T325	Yes	T14,T11,T325	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T46,T11	Yes	T14,T46,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T61,T46,T251	Yes	T61,T46,T251	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T166	Yes	T80,T81,T166	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T166	Yes	T80,T81,T166	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T61,T46,T251	Yes	T61,T46,T251	OUTPUT
cio_rx_i	Yes	Yes	T14,T16,T356	Yes	T14,T16,T356	INPUT
cio_tx_o	Yes	Yes	T14,T16,T356	Yes	T14,T16,T356	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T325,T16	Yes	T14,T325,T16	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T325,T16	Yes	T14,T325,T16	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T325,T16	Yes	T14,T325,T16	OUTPUT
intr_tx_done_o	Yes	Yes	T14,T325,T16	Yes	T14,T325,T16	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T325,T16	Yes	T14,T325,T16	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T325,T337,T330	Yes	T325,T337,T330	OUTPUT

*Tests covering at least one bit in the range