Unified Coverage Report :: Module :: tlul_err

Module : tlul_err

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_err	83.23	96.15	74.29			62.50	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	57	17	17	100.00
CONT_ASSIGN	96	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
54	1	1
57	1	1
58	1	1
59	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
70	1	1
72	1	1
74	1	1
78	1	1
79	1	1
80	1	1
90	1	1
91	1	1
92	1	1
96	1	1

---

Cond Coverage for Module : tlul_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T75,T52,T76

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T71,T77,T464
0	1	0	Covered	T559,T772,T430
1	0	0	Covered	T1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T71,T77,T464
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T71,T77,T464
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T75,T52,T76
1	0	0	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T75,T52,T76

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T71,T72,T77
1	Covered	T71,T72,T73

 LINE       74
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T71,T72,T77
1	Covered	T71,T72,T73

 LINE       96
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T71,T77,T464
1	0	1	Covered	T71,T77,T464
1	1	0	Covered	T71,T77,T464
1	1	1	Covered	T1,T2,T3

 LINE       96
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T75,T52,T76
1	0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	61	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if (tl_i.a_valid)
-2-:	62	case (tl_i.a_size)
-3-:	72	(tl_i.a_address[1]) ? 
-4-:	74	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T71,T72,T73
1	'h1	1	-	Covered	T71,T72,T73
1	'h1	0	-	Covered	T71,T72,T77
1	'h1	-	1	Covered	T71,T72,T73
1	'h1	-	0	Covered	T71,T72,T77
1	'h00000002	-	-	Covered	T1,T2,T3
1	default	-	-	Covered	T71,T77,T464
0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	9862	9862	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9862	9862	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T43	4	4	0	0
T45	4	4	0	0
T61	4	4	0	0
T83	4	4	0	0