Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T61,T62,T233	Yes	T61,T62,T233	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T43	Yes	T1,T2,T43	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T1,T2,T43	Yes	T1,T2,T43	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T1,T2,T43	Yes	T1,T2,T43	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	INPUT
tl_uart0_i.d_error	Yes	Yes	T71,T73,T77	Yes	T71,T72,T73	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	INPUT
tl_uart0_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T263,*T76,*T71	Yes	T263,T76,T71	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T2,*T43,*T44	Yes	T2,T43,T44	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T11,T325,T339	Yes	T11,T325,T339	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T11,T325,T339	Yes	T11,T325,T339	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T46,T11,T325	Yes	T46,T11,T325	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T46,T11,T325	Yes	T46,T11,T325	INPUT
tl_uart1_i.d_error	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T11,T325,T339	Yes	T11,T325,T339	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T325,T251	Yes	T46,T11,T325	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T11,T325,T251	Yes	T46,T11,T325	INPUT
tl_uart1_i.d_sink	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T76,*T71,*T73	Yes	T76,T71,T73	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T11,*T325,*T339	Yes	T11,T325,T339	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T46,T11,T325	Yes	T46,T11,T325	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T152,T11,T325	Yes	T152,T11,T325	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T152,T11,T325	Yes	T152,T11,T325	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T152,T46,T11	Yes	T152,T46,T11	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T152,T46,T11	Yes	T152,T46,T11	INPUT
tl_uart2_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T77,T555	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T152,T11,T325	Yes	T152,T11,T325	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T11,T325	Yes	T152,T46,T11	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T152,T11,T325	Yes	T152,T46,T11	INPUT
tl_uart2_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T76,*T71,*T77	Yes	T76,T71,T72	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T77	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T152,*T11,*T325	Yes	T152,T11,T325	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T152,T46,T11	Yes	T152,T46,T11	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T14,T11,T325	Yes	T14,T11,T325	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T14,T11,T325	Yes	T14,T11,T325	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T14,T46,T11	Yes	T14,T46,T11	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T14,T46,T11	Yes	T14,T46,T11	INPUT
tl_uart3_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T14,T11,T325	Yes	T14,T11,T325	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T14,T11,T325	Yes	T14,T46,T11	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T14,T11,T325	Yes	T14,T46,T11	INPUT
tl_uart3_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T76,*T71,*T72	Yes	T76,T71,T72	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T14,*T11,*T325	Yes	T14,T11,T325	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T14,T46,T11	Yes	T14,T46,T11	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T220,T224,T225	Yes	T220,T224,T225	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T220,T224,T225	Yes	T220,T224,T225	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T220,T224,T225	Yes	T220,T224,T225	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T220,T224,T225	Yes	T220,T224,T225	INPUT
tl_i2c0_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T224,T225,T11	Yes	T224,T225,T11	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T220,T224,T225	Yes	T220,T224,T225	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T220,T224,T225	Yes	T220,T224,T225	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T52,*T76,*T71	Yes	T52,T76,T71	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T220,*T224,*T225	Yes	T220,T224,T225	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T220,T224,T225	Yes	T220,T224,T225	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T220,T11,T344	Yes	T220,T11,T344	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T220,T11,T344	Yes	T220,T11,T344	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T220,T46,T11	Yes	T220,T46,T11	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T220,T46,T11	Yes	T220,T46,T11	INPUT
tl_i2c1_i.d_error	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T11,T344,T289	Yes	T11,T344,T289	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T220,T11,T344	Yes	T220,T46,T11	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T220,T11,T344	Yes	T220,T46,T11	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T71,T73,T77	Yes	T71,T72,T73	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T52,*T76,*T71	Yes	T52,T76,T71	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T71,T73,T77	Yes	T71,T72,T73	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T220,*T11,*T344	Yes	T220,T11,T344	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T220,T46,T11	Yes	T220,T46,T11	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T104,T220,T228	Yes	T104,T220,T228	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T104,T220,T228	Yes	T104,T220,T228	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T104,T220,T228	Yes	T104,T220,T228	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T104,T220,T228	Yes	T104,T220,T228	INPUT
tl_i2c2_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T104,T228,T11	Yes	T104,T228,T11	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T104,T220,T228	Yes	T104,T220,T228	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T104,T220,T228	Yes	T104,T220,T228	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T52,*T76,*T71	Yes	T52,T76,T71	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T77	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T104,*T220,*T228	Yes	T104,T220,T228	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T104,T220,T228	Yes	T104,T220,T228	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T226,T11,T227	Yes	T226,T11,T227	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T226,T11,T227	Yes	T226,T11,T227	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T226,T46,T11	Yes	T226,T46,T11	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T226,T46,T11	Yes	T226,T46,T11	INPUT
tl_pattgen_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T77	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T226,T11,T227	Yes	T226,T11,T227	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T226,T11,T227	Yes	T226,T46,T11	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T226,T11,T227	Yes	T226,T46,T11	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T71,*T72,*T77	Yes	T71,T72,T73	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T226,*T11,*T227	Yes	T226,T11,T227	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T226,T46,T11	Yes	T226,T46,T11	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T112,T11,T154	Yes	T112,T11,T154	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T112,T11,T154	Yes	T112,T11,T154	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T112,T46,T11	Yes	T112,T46,T11	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T112,T46,T11	Yes	T112,T46,T11	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T73,T77	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T112,T11,T154	Yes	T112,T11,T154	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T112,T11,T154	Yes	T112,T46,T11	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T112,T11,T154	Yes	T112,T46,T11	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T52,*T71,*T77	Yes	T52,T71,T73	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T112,*T11,*T154	Yes	T112,T11,T154	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T112,T46,T11	Yes	T112,T46,T11	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T49,T24,T25	Yes	T49,T24,T25	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T24,T25	Yes	T112,T46,T11	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T49,T24,T25	Yes	T112,T46,T11	INPUT
tl_gpio_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T77	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T52,*T76,*T71	Yes	T52,T76,T71	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T7,T82,T220	Yes	T7,T82,T220	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T7,T82,T220	Yes	T7,T82,T220	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T7,T82,T220	Yes	T7,T82,T220	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T7,T82,T220	Yes	T7,T82,T220	INPUT
tl_spi_device_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T7,T82,T220	Yes	T7,T82,T220	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T82,T220	Yes	T7,T82,T220	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T7,T82,T220	Yes	T7,T82,T220	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T213,*T71,*T72	Yes	T213,T71,T72	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T7,*T82,*T220	Yes	T7,T82,T220	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T7,T82,T220	Yes	T7,T82,T220	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T260,T112,T257	Yes	T260,T112,T257	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T260,T112,T257	Yes	T260,T112,T257	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T260,T112,T257	Yes	T260,T112,T257	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T260,T112,T257	Yes	T260,T112,T257	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T260,T257,T776	Yes	T260,T257,T776	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T260,T112,T257	Yes	T260,T112,T257	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T260,T112,T257	Yes	T260,T112,T257	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T213,*T71,*T77	Yes	T213,T71,T72	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T71,T73,T77	Yes	T71,T72,T77	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T260,*T112,*T257	Yes	T260,T112,T257	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T260,T112,T257	Yes	T260,T112,T257	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T71,T77,T131	Yes	T71,T77,T131	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T71,T77,T131	Yes	T71,T72,T77	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T52,*T71,*T77	Yes	T52,T71,T72	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T43	Yes	T4,T5,T43	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T5,T43	Yes	T4,T5,T43	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T52,*T71,*T77	Yes	T52,T71,T72	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T77,T131	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T83	Yes	T1,T2,T83	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T83	Yes	T1,T2,T83	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T83,T45	Yes	T2,T83,T45	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T77	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T71,*T77,*T131	Yes	T74,T157,T761	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T83	Yes	T1,T2,T83	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T71,T73,T77	Yes	T71,T72,T73	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T52,*T71,*T73	Yes	T52,T71,T72	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T7,*T74,*T157	Yes	T7,T74,T157	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T6,*T158,*T7	Yes	T6,T158,T7	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T71,T73,T77	Yes	T71,T73,T77	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T77	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T71,T77,T131	Yes	T71,T72,T73	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T3,T4	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T6,T43,T44	Yes	T6,T43,T44	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T6,T43,T44	Yes	T6,T43,T44	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T6,T43,T44	Yes	T6,T43,T44	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T6,T43,T44	Yes	T6,T43,T44	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T6,T43,T44	Yes	T6,T43,T44	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T59,T197	Yes	T6,T59,T46	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T6,T43,T44	Yes	T6,T43,T44	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T319,*T320,*T321	Yes	T319,T320,T321	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T6,*T158,*T7	Yes	T6,T43,T44	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T6,T43,T44	Yes	T6,T43,T44	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T44,T18,T133	Yes	T44,T18,T133	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T18,T133	Yes	T44,T18,T133	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T71,T77,T131	Yes	T71,T72,T73	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T213,*T71,*T77	Yes	T213,T71,T72	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T1,T5,T61	Yes	T1,T5,T61	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T1,T5,T61	Yes	T1,T5,T61	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T1,T5,T61	Yes	T1,T5,T61	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T1,T5,T61	Yes	T1,T5,T61	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T71,T72,T131	Yes	T71,T72,T131	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T1,T5,T61	Yes	T1,T5,T61	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T5,T61	Yes	T1,T5,T61	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T1,T5,T61	Yes	T1,T5,T61	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T1,*T5,*T61	Yes	T1,T5,T61	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T1,T5,T61	Yes	T1,T5,T61	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T3,T43,T44	Yes	T3,T43,T44	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T3,T43,T44	Yes	T3,T43,T44	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T3,T43,T44	Yes	T3,T43,T44	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T3,T43,T44	Yes	T3,T43,T44	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T3,T119,T120	Yes	T3,T119,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T40,T41	Yes	T3,T43,T44	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T3,T40,T41	Yes	T3,T43,T44	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T213,*T71,*T72	Yes	T213,T71,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T3,*T119,*T120	Yes	T3,T288,T445	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T3,T43,T44	Yes	T3,T43,T44	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T75,*T211,*T212	Yes	T75,T211,T212	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T71,T73,T77	Yes	T71,T77,T131	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T71,*T77,*T131	Yes	T765,T766,T71	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T77,T131	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T61	Yes	T4,T5,T61	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T4,T5,T61	Yes	T4,T5,T61	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T18,T34	Yes	T4,T18,T34	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T18,T34	Yes	T4,T18,T34	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T4,T18,T34	Yes	T4,T18,T34	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T4,T18,T34	Yes	T4,T18,T34	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T18,T34	Yes	T4,T18,T34	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T18,T34	Yes	T4,T18,T34	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T34,T261	Yes	T4,T18,T34	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T76,*T213,*T71	Yes	T76,T213,T71	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T18,*T34	Yes	T4,T18,T34	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T4,T18,T34	Yes	T4,T18,T34	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T18,T111,T112	Yes	T18,T111,T112	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T18,T111,T112	Yes	T18,T111,T112	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T18,T111,T112	Yes	T18,T111,T112	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T18,T111,T112	Yes	T18,T111,T112	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T111,T57	Yes	T18,T111,T57	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T111,T112	Yes	T18,T111,T112	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T18,T111,T112	Yes	T18,T111,T112	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T71,*T77,*T131	Yes	T71,T72,T73	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T18,*T111,*T112	Yes	T18,T111,T112	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T18,T111,T112	Yes	T18,T111,T112	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T7,*T74,*T75	Yes	T7,T74,T75	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T75,T52,T76	Yes	T75,T52,T76	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T71,T72,T73	Yes	T71,T73,T77	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T73	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T71,*T77,*T131	Yes	T71,T72,T73	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T71,*T72,*T73	Yes	T71,T72,T73	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range