Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1121589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36637723

1

T1

15594

T2

19364

T3

11329

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26348554	1			T1	7082		T2	12152		T3	5422
values[0x0]	10288305	1			T1	8512		T2	7212		T3	5907
values[0x1]	1122453	1			T1	1249		T2	2414		T3	475

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37750675

1

T1

16843

T2

21778

T3

11804

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18866332	1			T1	8422		T2	10889		T3	5902
valid_sources[0x01]	18865451	1			T1	8421		T2	10889		T3	5902
valid_sources[0x02]	265	1			T190	4		T49	58		T50	43
valid_sources[0x03]	263	1			T100	2		T190	1		T49	65
valid_sources[0x04]	298	1			T49	49		T50	52		T51	43
valid_sources[0x05]	227	1			T49	46		T50	48		T51	47
valid_sources[0x06]	274	1			T49	51		T50	52		T51	52
valid_sources[0x07]	2090	1			T99	39		T190	1		T17	1
valid_sources[0x08]	235	1			T49	47		T50	44		T51	40
valid_sources[0x09]	277	1			T189	1		T49	39		T50	65
valid_sources[0x0a]	2264	1			T190	1		T17	6		T49	45
valid_sources[0x0b]	262	1			T100	2		T190	1		T49	52
valid_sources[0x0c]	312	1			T100	2		T190	3		T49	45
valid_sources[0x0d]	2277	1			T100	2		T190	1		T49	48
valid_sources[0x0e]	269	1			T100	1		T190	2		T17	2
valid_sources[0x0f]	359	1			T17	1		T49	43		T50	46
valid_sources[0x10]	255	1			T190	1		T49	66		T50	39
valid_sources[0x11]	274	1			T100	1		T189	1		T17	1
valid_sources[0x12]	397	1			T189	1		T49	51		T50	60
valid_sources[0x13]	252	1			T189	8		T49	41		T50	47
valid_sources[0x14]	402	1			T17	1		T49	44		T50	51
valid_sources[0x15]	383	1			T190	2		T49	53		T50	54
valid_sources[0x16]	247	1			T189	3		T17	1		T49	49
valid_sources[0x17]	290	1			T100	1		T17	1		T49	64
valid_sources[0x18]	234	1			T17	1		T49	54		T50	55
valid_sources[0x19]	263	1			T189	1		T49	50		T50	58
valid_sources[0x1a]	229	1			T49	55		T50	41		T51	45
valid_sources[0x1b]	264	1			T100	2		T17	1		T49	60
valid_sources[0x1c]	249	1			T100	3		T49	60		T50	41
valid_sources[0x1d]	302	1			T190	1		T17	1		T49	43
valid_sources[0x1e]	222	1			T100	2		T49	41		T50	39
valid_sources[0x1f]	467	1			T17	1		T49	43		T50	65
valid_sources[0x20]	395	1			T49	54		T50	57		T51	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26348554

1

T1

7082

T2

12152

T3

5422

values[0x0]

all_enables

biggest_size

10283887

1

T1

8512

T2

7212

T3

5907

values[0x1]

all_enables

biggest_size

5282

1

T99

19

T100

16

T101

16