| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 40.71 |
40.71 |
44.96 |
44.96 |
43.00 |
43.00 |
31.76 |
31.76 |
|
|
57.86 |
57.86 |
59.44 |
59.44 |
7.24 |
7.24 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1988017989 |
| 49.74 |
9.03 |
45.03 |
0.07 |
43.07 |
0.08 |
35.78 |
4.02 |
|
|
57.87 |
0.01 |
59.44 |
0.00 |
57.24 |
50.00 |
/workspace/coverage/default/1.chip_sw_alert_test.2683603476 |
| 55.83 |
6.09 |
55.67 |
10.64 |
48.87 |
5.80 |
40.64 |
4.86 |
|
|
61.10 |
3.24 |
63.99 |
4.55 |
64.69 |
7.46 |
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.357255758 |
| 61.11 |
5.28 |
66.84 |
11.17 |
56.07 |
7.20 |
44.02 |
3.38 |
|
|
70.90 |
9.79 |
64.16 |
0.17 |
64.69 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.909069242 |
| 64.51 |
3.40 |
73.00 |
6.16 |
62.71 |
6.64 |
44.37 |
0.35 |
|
|
77.77 |
6.87 |
64.51 |
0.35 |
64.69 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1502685443 |
| 67.18 |
2.67 |
73.00 |
0.01 |
62.73 |
0.02 |
60.35 |
15.98 |
|
|
77.78 |
0.02 |
64.51 |
0.00 |
64.69 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.255495353 |
| 68.94 |
1.76 |
74.85 |
1.85 |
65.14 |
2.41 |
64.73 |
4.38 |
|
|
79.53 |
1.74 |
64.69 |
0.17 |
64.69 |
0.00 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.211253893 |
| 70.35 |
1.41 |
76.20 |
1.35 |
66.28 |
1.14 |
65.74 |
1.01 |
|
|
80.84 |
1.31 |
68.36 |
3.67 |
64.69 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2447468699 |
| 71.66 |
1.31 |
78.56 |
2.35 |
68.28 |
2.00 |
66.95 |
1.21 |
|
|
83.16 |
2.31 |
68.36 |
0.00 |
64.69 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.978037554 |
| 72.97 |
1.31 |
78.59 |
0.03 |
68.28 |
0.00 |
74.77 |
7.82 |
|
|
83.16 |
0.00 |
68.36 |
0.00 |
64.69 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3070377154 |
| 74.16 |
1.18 |
80.41 |
1.82 |
69.15 |
0.88 |
77.81 |
3.04 |
|
|
83.81 |
0.66 |
69.06 |
0.70 |
64.69 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_virus.1208068063 |
| 75.15 |
0.99 |
81.40 |
1.00 |
69.68 |
0.53 |
77.83 |
0.02 |
|
|
84.38 |
0.57 |
72.90 |
3.85 |
64.69 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.577503505 |
| 75.80 |
0.65 |
82.67 |
1.27 |
70.69 |
1.01 |
78.29 |
0.46 |
|
|
85.57 |
1.19 |
72.90 |
0.00 |
64.69 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.259445654 |
| 76.45 |
0.64 |
83.06 |
0.40 |
71.46 |
0.77 |
78.43 |
0.14 |
|
|
86.03 |
0.45 |
75.00 |
2.10 |
64.69 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2271130879 |
| 76.99 |
0.55 |
83.88 |
0.81 |
72.26 |
0.81 |
78.44 |
0.01 |
|
|
86.60 |
0.57 |
75.00 |
0.00 |
65.79 |
1.10 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.508484694 |
| 77.51 |
0.51 |
83.92 |
0.05 |
72.29 |
0.02 |
80.14 |
1.69 |
|
|
86.63 |
0.03 |
75.17 |
0.17 |
66.89 |
1.10 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.483541534 |
| 77.98 |
0.48 |
84.20 |
0.28 |
72.57 |
0.28 |
80.14 |
0.00 |
|
|
86.84 |
0.21 |
77.27 |
2.10 |
66.89 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2715153387 |
| 78.46 |
0.48 |
84.48 |
0.28 |
72.83 |
0.26 |
80.14 |
0.00 |
|
|
87.06 |
0.22 |
79.37 |
2.10 |
66.89 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1065183361 |
| 78.94 |
0.48 |
84.77 |
0.28 |
73.10 |
0.26 |
80.14 |
0.00 |
|
|
87.28 |
0.22 |
81.47 |
2.10 |
66.89 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1949738528 |
| 79.35 |
0.41 |
85.55 |
0.78 |
73.94 |
0.84 |
80.79 |
0.65 |
|
|
87.46 |
0.19 |
81.47 |
0.00 |
66.89 |
0.00 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1581544171 |
| 79.67 |
0.32 |
85.82 |
0.27 |
74.05 |
0.11 |
81.96 |
1.17 |
|
|
87.66 |
0.19 |
81.64 |
0.17 |
66.89 |
0.00 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.267356975 |
| 79.93 |
0.26 |
85.83 |
0.01 |
74.05 |
0.01 |
82.62 |
0.67 |
|
|
87.66 |
0.00 |
81.64 |
0.00 |
67.76 |
0.88 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1054602890 |
| 80.19 |
0.26 |
85.83 |
0.00 |
74.05 |
0.00 |
82.62 |
0.00 |
|
|
87.66 |
0.00 |
81.64 |
0.00 |
69.30 |
1.54 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4111204684 |
| 80.41 |
0.22 |
85.94 |
0.11 |
74.14 |
0.08 |
82.65 |
0.03 |
|
|
87.73 |
0.07 |
82.69 |
1.05 |
69.30 |
0.00 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1759384397 |
| 80.60 |
0.19 |
86.28 |
0.34 |
74.33 |
0.19 |
82.99 |
0.34 |
|
|
88.02 |
0.29 |
82.69 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.720807150 |
| 80.79 |
0.19 |
86.37 |
0.09 |
74.34 |
0.01 |
84.03 |
1.04 |
|
|
88.02 |
0.00 |
82.69 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1514711722 |
| 80.97 |
0.18 |
86.46 |
0.10 |
74.79 |
0.46 |
84.04 |
0.01 |
|
|
88.54 |
0.52 |
82.69 |
0.00 |
69.30 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1137840202 |
| 81.13 |
0.16 |
86.46 |
0.00 |
74.80 |
0.01 |
84.79 |
0.75 |
|
|
88.54 |
0.00 |
82.69 |
0.00 |
69.52 |
0.22 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3692746523 |
| 81.29 |
0.15 |
86.81 |
0.35 |
75.06 |
0.26 |
84.97 |
0.18 |
|
|
88.68 |
0.14 |
82.69 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.3555775949 |
| 81.44 |
0.15 |
87.02 |
0.21 |
75.38 |
0.32 |
85.32 |
0.35 |
|
|
88.68 |
0.00 |
82.69 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1069862976 |
| 81.55 |
0.11 |
87.02 |
0.00 |
75.39 |
0.01 |
85.99 |
0.67 |
|
|
88.68 |
0.00 |
82.69 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.823215803 |
| 81.65 |
0.11 |
87.04 |
0.02 |
75.40 |
0.01 |
86.42 |
0.43 |
|
|
88.68 |
0.00 |
82.87 |
0.17 |
69.52 |
0.00 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.460550312 |
| 81.75 |
0.09 |
87.07 |
0.03 |
75.47 |
0.07 |
86.65 |
0.23 |
|
|
88.73 |
0.05 |
83.04 |
0.17 |
69.52 |
0.00 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3354749078 |
| 81.83 |
0.09 |
87.07 |
0.00 |
75.47 |
0.01 |
87.17 |
0.52 |
|
|
88.73 |
0.00 |
83.04 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1995875712 |
| 81.92 |
0.08 |
87.07 |
0.00 |
75.47 |
0.00 |
87.66 |
0.49 |
|
|
88.73 |
0.00 |
83.04 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3596693592 |
| 81.99 |
0.08 |
87.23 |
0.17 |
75.59 |
0.11 |
87.73 |
0.07 |
|
|
88.85 |
0.12 |
83.04 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4190862959 |
| 82.07 |
0.08 |
87.24 |
0.01 |
75.61 |
0.03 |
87.73 |
0.00 |
|
|
88.88 |
0.02 |
83.22 |
0.17 |
69.74 |
0.22 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1857172836 |
| 82.14 |
0.07 |
87.25 |
0.01 |
75.63 |
0.01 |
87.73 |
0.00 |
|
|
88.90 |
0.02 |
83.39 |
0.17 |
69.96 |
0.22 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3621665469 |
| 82.22 |
0.07 |
87.26 |
0.01 |
75.64 |
0.01 |
87.74 |
0.01 |
|
|
88.91 |
0.01 |
83.57 |
0.17 |
70.18 |
0.22 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2955420472 |
| 82.29 |
0.07 |
87.26 |
0.01 |
75.65 |
0.01 |
87.75 |
0.01 |
|
|
88.92 |
0.01 |
83.74 |
0.17 |
70.39 |
0.22 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3203048834 |
| 82.35 |
0.07 |
87.28 |
0.02 |
75.84 |
0.18 |
87.75 |
0.01 |
|
|
89.13 |
0.21 |
83.74 |
0.00 |
70.39 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2644060743 |
| 82.42 |
0.06 |
87.28 |
0.00 |
75.97 |
0.14 |
87.81 |
0.07 |
|
|
89.13 |
0.00 |
83.92 |
0.17 |
70.39 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1457584032 |
| 82.47 |
0.06 |
87.28 |
0.00 |
75.97 |
0.00 |
87.93 |
0.12 |
|
|
89.13 |
0.00 |
83.92 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.4284335447 |
| 82.53 |
0.05 |
87.28 |
0.00 |
75.97 |
0.00 |
88.24 |
0.31 |
|
|
89.13 |
0.00 |
83.92 |
0.00 |
70.61 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2593248528 |
| 82.58 |
0.05 |
87.32 |
0.04 |
76.18 |
0.20 |
88.24 |
0.00 |
|
|
89.19 |
0.06 |
83.92 |
0.00 |
70.61 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3355381206 |
| 82.62 |
0.05 |
87.32 |
0.00 |
76.18 |
0.01 |
88.30 |
0.05 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2452211226 |
| 82.66 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.32 |
0.03 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3859921177 |
| 82.70 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.56 |
0.24 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
71.05 |
0.00 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3129832346 |
| 82.74 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.57 |
0.01 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.707697946 |
| 82.78 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.01 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3446444837 |
| 82.82 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.01 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1626136336 |
| 82.85 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.697883980 |
| 82.89 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.2603524313 |
| 82.93 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1981430239 |
| 82.96 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.3341942489 |
| 83.00 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.3376795541 |
| 83.04 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.877600141 |
| 83.07 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1286637285 |
| 83.11 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032355277 |
| 83.15 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1008606446 |
| 83.18 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4199319053 |
| 83.22 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2399394796 |
| 83.26 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.3045065663 |
| 83.29 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2779266364 |
| 83.33 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.95833127 |
| 83.37 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.3190121761 |
| 83.40 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1335042735 |
| 83.44 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4204804100 |
| 83.47 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.936051978 |
| 83.51 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2338664184 |
| 83.55 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3501770501 |
| 83.58 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.59405308 |
| 83.62 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1351198433 |
| 83.66 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.2448680340 |
| 83.69 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.834011930 |
| 83.73 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.1871469707 |
| 83.77 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.49105368 |
| 83.80 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1407285796 |
| 83.84 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.616013443 |
| 83.88 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.4017906303 |
| 83.91 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2163397945 |
| 83.95 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3224808878 |
| 83.99 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3215335215 |
| 84.02 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1912127956 |
| 84.06 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2298089335 |
| 84.10 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2619978890 |
| 84.13 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3216885078 |
| 84.17 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.880573998 |
| 84.21 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1365941886 |
| 84.24 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.762267365 |
| 84.28 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2595458387 |
| 84.32 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4215108881 |
| 84.35 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.378520222 |
| 84.39 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2876863207 |
| 84.43 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2441963508 |
| 84.46 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1258880215 |
| 84.50 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.946245582 |
| 84.53 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.986594536 |
| 84.57 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3126985555 |
| 84.61 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1441279622 |
| 84.64 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.670902966 |
| 84.68 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250016360 |
| 84.72 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.568143593 |
| 84.75 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3697555326 |
| 84.79 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553041001 |
| 84.83 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1035766392 |
| 84.86 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1066538361 |
| 84.90 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238938059 |
| 84.94 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3909638825 |
| 84.97 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
84.65 |
0.22 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1564262822 |
| 85.01 |
0.04 |
87.32 |
0.00 |
76.18 |
0.00 |
88.58 |
0.00 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
84.87 |
0.22 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.4181144789 |
| 85.05 |
0.04 |
87.49 |
0.17 |
76.20 |
0.02 |
88.60 |
0.02 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1594829807 |
| 85.08 |
0.03 |
87.49 |
0.00 |
76.20 |
0.00 |
88.80 |
0.19 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3412419296 |
| 85.11 |
0.03 |
87.49 |
0.00 |
76.20 |
0.00 |
88.97 |
0.17 |
|
|
89.19 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3335819945 |
| 85.14 |
0.03 |
87.51 |
0.02 |
76.23 |
0.03 |
89.07 |
0.10 |
|
|
89.22 |
0.02 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1587856144 |
| 85.16 |
0.03 |
87.58 |
0.07 |
76.26 |
0.03 |
89.08 |
0.01 |
|
|
89.27 |
0.05 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1911045134 |
| 85.18 |
0.02 |
87.58 |
0.00 |
76.38 |
0.12 |
89.08 |
0.00 |
|
|
89.27 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2944717956 |
| 85.20 |
0.02 |
87.59 |
0.01 |
76.40 |
0.02 |
89.16 |
0.07 |
|
|
89.28 |
0.02 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.4152755177 |
| 85.22 |
0.02 |
87.59 |
0.00 |
76.40 |
0.00 |
89.27 |
0.11 |
|
|
89.28 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.163765351 |
| 85.24 |
0.02 |
87.59 |
0.00 |
76.50 |
0.10 |
89.27 |
0.00 |
|
|
89.28 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3715513551 |
| 85.25 |
0.02 |
87.59 |
0.00 |
76.61 |
0.10 |
89.27 |
0.00 |
|
|
89.28 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2120579373 |
| 85.27 |
0.02 |
87.59 |
0.00 |
76.61 |
0.00 |
89.37 |
0.10 |
|
|
89.28 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.1217211982 |
| 85.29 |
0.02 |
87.60 |
0.01 |
76.65 |
0.04 |
89.39 |
0.02 |
|
|
89.31 |
0.02 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1229759114 |
| 85.30 |
0.01 |
87.67 |
0.07 |
76.65 |
0.01 |
89.40 |
0.01 |
|
|
89.31 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4140920706 |
| 85.31 |
0.01 |
87.67 |
0.00 |
76.70 |
0.05 |
89.42 |
0.02 |
|
|
89.31 |
0.01 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2759294692 |
| 85.33 |
0.01 |
87.67 |
0.01 |
76.72 |
0.02 |
89.47 |
0.05 |
|
|
89.31 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1612197426 |
| 85.34 |
0.01 |
87.69 |
0.02 |
76.74 |
0.02 |
89.48 |
0.01 |
|
|
89.34 |
0.02 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1207984759 |
| 85.35 |
0.01 |
87.69 |
0.00 |
76.74 |
0.00 |
89.55 |
0.07 |
|
|
89.34 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_init.209174306 |
| 85.36 |
0.01 |
87.69 |
0.00 |
76.74 |
0.00 |
89.61 |
0.07 |
|
|
89.34 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2197864360 |
| 85.37 |
0.01 |
87.70 |
0.01 |
76.74 |
0.00 |
89.67 |
0.05 |
|
|
89.34 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_jtag_csr_rw.415199552 |
| 85.38 |
0.01 |
87.72 |
0.02 |
76.74 |
0.01 |
89.67 |
0.01 |
|
|
89.35 |
0.02 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.132910492 |
| 85.39 |
0.01 |
87.74 |
0.02 |
76.75 |
0.01 |
89.68 |
0.01 |
|
|
89.37 |
0.02 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.222439706 |
| 85.40 |
0.01 |
87.74 |
0.00 |
76.80 |
0.05 |
89.68 |
0.00 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.2416229857 |
| 85.40 |
0.01 |
87.75 |
0.01 |
76.82 |
0.02 |
89.70 |
0.02 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.2095668869 |
| 85.41 |
0.01 |
87.75 |
0.00 |
76.82 |
0.00 |
89.75 |
0.05 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1892272571 |
| 85.42 |
0.01 |
87.75 |
0.00 |
76.87 |
0.05 |
89.75 |
0.00 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1969715305 |
| 85.43 |
0.01 |
87.75 |
0.00 |
76.87 |
0.00 |
89.79 |
0.04 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2824144296 |
| 85.43 |
0.01 |
87.75 |
0.00 |
76.91 |
0.04 |
89.79 |
0.00 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.590156483 |
| 85.44 |
0.01 |
87.78 |
0.03 |
76.91 |
0.01 |
89.79 |
0.00 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2256443888 |
| 85.44 |
0.01 |
87.80 |
0.02 |
76.91 |
0.00 |
89.80 |
0.01 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_rma.3528392868 |
| 85.45 |
0.01 |
87.80 |
0.00 |
76.94 |
0.03 |
89.80 |
0.00 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.4057735088 |
| 85.45 |
0.01 |
87.80 |
0.00 |
76.94 |
0.00 |
89.83 |
0.03 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1807164538 |
| 85.46 |
0.01 |
87.80 |
0.00 |
76.94 |
0.00 |
89.86 |
0.03 |
|
|
89.37 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3444304045 |
| 85.46 |
0.01 |
87.80 |
0.00 |
76.96 |
0.02 |
89.86 |
0.00 |
|
|
89.38 |
0.01 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3139659317 |
| 85.47 |
0.01 |
87.80 |
0.00 |
76.96 |
0.00 |
89.88 |
0.02 |
|
|
89.38 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.2235357278 |
| 85.47 |
0.01 |
87.80 |
0.01 |
76.97 |
0.01 |
89.89 |
0.01 |
|
|
89.38 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3556338891 |
| 85.47 |
0.01 |
87.80 |
0.00 |
76.97 |
0.00 |
89.90 |
0.01 |
|
|
89.39 |
0.01 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.989269666 |
| 85.48 |
0.01 |
87.80 |
0.00 |
76.98 |
0.01 |
89.90 |
0.01 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3553744870 |
| 85.48 |
0.01 |
87.81 |
0.01 |
76.98 |
0.00 |
89.91 |
0.01 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3879276493 |
| 85.48 |
0.01 |
87.81 |
0.00 |
77.00 |
0.01 |
89.91 |
0.00 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.1956427370 |
| 85.48 |
0.01 |
87.81 |
0.00 |
77.00 |
0.00 |
89.93 |
0.01 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1003312567 |
| 85.49 |
0.01 |
87.81 |
0.00 |
77.00 |
0.00 |
89.94 |
0.01 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2709524342 |
| 85.49 |
0.01 |
87.81 |
0.00 |
77.01 |
0.01 |
89.94 |
0.00 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3701626105 |
| 85.49 |
0.01 |
87.81 |
0.00 |
77.02 |
0.01 |
89.94 |
0.00 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4117052021 |
| 85.49 |
0.01 |
87.81 |
0.00 |
77.03 |
0.01 |
89.94 |
0.00 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2613472561 |
| 85.49 |
0.01 |
87.81 |
0.00 |
77.04 |
0.01 |
89.94 |
0.00 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3644681515 |
| 85.49 |
0.01 |
87.81 |
0.00 |
77.05 |
0.01 |
89.94 |
0.00 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2868217354 |
| 85.50 |
0.01 |
87.81 |
0.00 |
77.05 |
0.00 |
89.95 |
0.01 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3480070814 |
| 85.50 |
0.01 |
87.81 |
0.00 |
77.05 |
0.00 |
89.96 |
0.01 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2102956524 |
| 85.50 |
0.01 |
87.81 |
0.00 |
77.05 |
0.00 |
89.97 |
0.01 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2106799875 |
| 85.50 |
0.01 |
87.81 |
0.00 |
77.05 |
0.00 |
89.98 |
0.01 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.902988745 |
| 85.50 |
0.01 |
87.81 |
0.00 |
77.05 |
0.00 |
89.99 |
0.01 |
|
|
89.39 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.953606827 |
| 85.50 |
0.01 |
87.81 |
0.00 |
77.05 |
0.00 |
89.99 |
0.00 |
|
|
89.40 |
0.01 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_tap_straps_dev.4197498827 |
| 85.51 |
0.01 |
87.81 |
0.00 |
77.06 |
0.01 |
89.99 |
0.00 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2206941932 |
| 85.51 |
0.01 |
87.81 |
0.00 |
77.06 |
0.01 |
89.99 |
0.00 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.1118647925 |
| 85.51 |
0.01 |
87.81 |
0.00 |
77.07 |
0.01 |
89.99 |
0.00 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1929498433 |
| 85.51 |
0.01 |
87.81 |
0.00 |
77.07 |
0.00 |
89.99 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.194454043 |
| 85.51 |
0.01 |
87.81 |
0.00 |
77.07 |
0.00 |
90.00 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2611177058 |
| 85.51 |
0.01 |
87.81 |
0.00 |
77.07 |
0.00 |
90.01 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_raw_unlock.3121771732 |
| 85.51 |
0.01 |
87.81 |
0.01 |
77.07 |
0.00 |
90.01 |
0.00 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1675049966 |
| 85.51 |
0.01 |
87.82 |
0.01 |
77.07 |
0.00 |
90.01 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2742146 |
| 85.51 |
0.01 |
87.82 |
0.00 |
77.07 |
0.00 |
90.02 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1154042599 |
| 85.51 |
0.01 |
87.82 |
0.00 |
77.07 |
0.00 |
90.02 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2611376067 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.07 |
0.00 |
90.02 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2828273423 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.07 |
0.00 |
90.03 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1575215601 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.07 |
0.00 |
90.03 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2727091871 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.07 |
0.01 |
90.03 |
0.00 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3320299142 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.08 |
0.01 |
90.03 |
0.00 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3596606486 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.08 |
0.01 |
90.03 |
0.00 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3117038579 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.08 |
0.01 |
90.03 |
0.00 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2330959948 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.09 |
0.01 |
90.03 |
0.00 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1106516516 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.09 |
0.00 |
90.04 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_aes_enc.2481708327 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.09 |
0.00 |
90.04 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.3978957145 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.09 |
0.00 |
90.04 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.197235630 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.09 |
0.00 |
90.04 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2331717883 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.09 |
0.00 |
90.05 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3074878202 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.09 |
0.00 |
90.05 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3688431678 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.09 |
0.00 |
90.05 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2030488802 |
| 85.52 |
0.01 |
87.82 |
0.00 |
77.09 |
0.00 |
90.05 |
0.01 |
|
|
89.40 |
0.00 |
83.92 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.952620702 |
| Name |
| /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.566871522 |
| /workspace/coverage/default/0.chip_sival_flash_info_access.900626031 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.196821130 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.106116581 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.1641961324 |
| /workspace/coverage/default/0.chip_sw_aes_idle.2184707182 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.2388640683 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.2124417561 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.483366861 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1781380768 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2736924649 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2145893141 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3047619925 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2780322656 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2884691036 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3936279941 |
| /workspace/coverage/default/0.chip_sw_alert_test.646391053 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.3806139653 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1341877044 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2385189764 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1334931987 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2170639085 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2158604178 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.121591370 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2320678011 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.764089071 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3524758816 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3198027418 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1451092920 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.348046955 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3378594684 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1185112904 |
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| /workspace/coverage/default/52.chip_sw_all_escalation_resets.3652588330 |
| /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4112563149 |
| /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.438382265 |
| /workspace/coverage/default/54.chip_sw_all_escalation_resets.323423138 |
| /workspace/coverage/default/56.chip_sw_all_escalation_resets.875673311 |
| /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604132182 |
| /workspace/coverage/default/57.chip_sw_all_escalation_resets.4236114838 |
| /workspace/coverage/default/58.chip_sw_all_escalation_resets.366074047 |
| /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2291205819 |
| /workspace/coverage/default/6.chip_sw_all_escalation_resets.3683692598 |
| /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1210065176 |
| /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2334729274 |
| /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1169959161 |
| /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196967227 |
| /workspace/coverage/default/60.chip_sw_all_escalation_resets.753399729 |
| /workspace/coverage/default/61.chip_sw_all_escalation_resets.3577065611 |
| /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333428335 |
| /workspace/coverage/default/62.chip_sw_all_escalation_resets.712094319 |
| /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.675937332 |
| /workspace/coverage/default/64.chip_sw_all_escalation_resets.3462861824 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2957475474 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2688858483 |
| /workspace/coverage/default/66.chip_sw_all_escalation_resets.1306223613 |
| /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.861073642 |
| /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1471092548 |
| /workspace/coverage/default/69.chip_sw_all_escalation_resets.1759827617 |
| /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3713580390 |
| /workspace/coverage/default/7.chip_sw_all_escalation_resets.2524357340 |
| /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3756218928 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3120586832 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3485283114 |
| /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.10753886 |
| /workspace/coverage/default/70.chip_sw_all_escalation_resets.2044648279 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.4091512340 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1853405742 |
| /workspace/coverage/default/72.chip_sw_all_escalation_resets.56025891 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3667595384 |
| /workspace/coverage/default/73.chip_sw_all_escalation_resets.3007751556 |
| /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911397241 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.1636503224 |
| /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646736323 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4008265284 |
| /workspace/coverage/default/76.chip_sw_all_escalation_resets.255652197 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.383294113 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.1335500865 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878752818 |
| /workspace/coverage/default/78.chip_sw_all_escalation_resets.708999776 |
| /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.404598224 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.4132861100 |
| /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.410553481 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.353253860 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3433986326 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2778040084 |
| /workspace/coverage/default/80.chip_sw_all_escalation_resets.1310006139 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3109594465 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.2324097482 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1313290563 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1915516385 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.883757344 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196812461 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.661986299 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2849770567 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.3647461817 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1758629285 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.821094762 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.4199145912 |
| /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2618606315 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.2195189802 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.545796706 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.446715004 |
| /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.549163075 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1882803527 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.2376324183 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.3742065466 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.325797301 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.2362478035 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.1472255928 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.2382975340 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.2320383271 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.4150311657 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.4131529830 |
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.670755234 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.784049982 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1706073002 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.507312334 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1494586566 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1131544435 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3526503971 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.41387924 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1988017989 |
|
|
Aug 14 06:17:10 PM PDT 24 |
Aug 14 06:26:37 PM PDT 24 |
5323805590 ps |
| T2 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1229759114 |
|
|
Aug 14 05:59:10 PM PDT 24 |
Aug 14 06:11:51 PM PDT 24 |
4826440021 ps |
| T3 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.25828448 |
|
|
Aug 14 05:56:27 PM PDT 24 |
Aug 14 06:02:52 PM PDT 24 |
3138411246 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3701626105 |
|
|
Aug 14 05:46:51 PM PDT 24 |
Aug 14 05:54:27 PM PDT 24 |
4878737484 ps |
| T34 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1612197426 |
|
|
Aug 14 06:09:26 PM PDT 24 |
Aug 14 06:32:55 PM PDT 24 |
9056244132 ps |
| T103 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.4045106094 |
|
|
Aug 14 05:50:18 PM PDT 24 |
Aug 14 06:09:03 PM PDT 24 |
6066199687 ps |
| T4 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3692746523 |
|
|
Aug 14 05:51:20 PM PDT 24 |
Aug 14 06:13:40 PM PDT 24 |
12148713432 ps |
| T5 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2709524342 |
|
|
Aug 14 05:52:50 PM PDT 24 |
Aug 14 06:25:12 PM PDT 24 |
9404222684 ps |
| T72 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2735759658 |
|
|
Aug 14 06:04:42 PM PDT 24 |
Aug 14 06:17:27 PM PDT 24 |
4047686950 ps |
| T92 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.4284335447 |
|
|
Aug 14 06:13:46 PM PDT 24 |
Aug 14 06:25:20 PM PDT 24 |
5820297088 ps |
| T166 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2278625088 |
|
|
Aug 14 06:11:30 PM PDT 24 |
Aug 14 06:15:58 PM PDT 24 |
3462162060 ps |
| T93 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.483541534 |
|
|
Aug 14 06:13:45 PM PDT 24 |
Aug 14 06:23:24 PM PDT 24 |
6097957240 ps |
| T285 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3634318076 |
|
|
Aug 14 05:55:32 PM PDT 24 |
Aug 14 06:00:20 PM PDT 24 |
3240723548 ps |
| T164 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3354749078 |
|
|
Aug 14 06:09:40 PM PDT 24 |
Aug 14 06:20:24 PM PDT 24 |
5898328254 ps |
| T25 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2415446890 |
|
|
Aug 14 06:05:57 PM PDT 24 |
Aug 14 07:08:18 PM PDT 24 |
26768721996 ps |
| T179 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1225340624 |
|
|
Aug 14 06:04:01 PM PDT 24 |
Aug 14 06:09:11 PM PDT 24 |
2395377416 ps |
| T73 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1807164538 |
|
|
Aug 14 05:51:05 PM PDT 24 |
Aug 14 06:02:12 PM PDT 24 |
4698996256 ps |
| T180 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.2680093805 |
|
|
Aug 14 06:11:25 PM PDT 24 |
Aug 14 06:18:47 PM PDT 24 |
2928136300 ps |
| T88 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3131190547 |
|
|
Aug 14 05:56:07 PM PDT 24 |
Aug 14 06:03:30 PM PDT 24 |
18963773648 ps |
| T67 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.211253893 |
|
|
Aug 14 05:59:45 PM PDT 24 |
Aug 14 06:59:19 PM PDT 24 |
15958695510 ps |
| T232 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3859921177 |
|
|
Aug 14 06:15:37 PM PDT 24 |
Aug 14 06:27:02 PM PDT 24 |
4893693050 ps |
| T155 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.909069242 |
|
|
Aug 14 05:49:37 PM PDT 24 |
Aug 14 06:01:16 PM PDT 24 |
3946627180 ps |
| T74 |
/workspace/coverage/default/1.chip_tap_straps_dev.716464500 |
|
|
Aug 14 05:57:15 PM PDT 24 |
Aug 14 05:59:43 PM PDT 24 |
2508745566 ps |
| T124 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3297799181 |
|
|
Aug 14 05:51:54 PM PDT 24 |
Aug 14 05:56:15 PM PDT 24 |
3298190973 ps |
| T89 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1441279622 |
|
|
Aug 14 06:17:37 PM PDT 24 |
Aug 14 06:24:39 PM PDT 24 |
3959408824 ps |
| T134 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.340483355 |
|
|
Aug 14 05:49:39 PM PDT 24 |
Aug 14 06:07:31 PM PDT 24 |
8116477990 ps |
| T162 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.707697946 |
|
|
Aug 14 06:15:55 PM PDT 24 |
Aug 14 06:23:38 PM PDT 24 |
5946345474 ps |
| T68 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3980866757 |
|
|
Aug 14 06:02:06 PM PDT 24 |
Aug 14 07:06:02 PM PDT 24 |
15715321144 ps |
| T37 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2447468699 |
|
|
Aug 14 05:54:54 PM PDT 24 |
Aug 14 06:01:20 PM PDT 24 |
7839092200 ps |
| T119 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.1768582460 |
|
|
Aug 14 05:57:51 PM PDT 24 |
Aug 14 06:02:24 PM PDT 24 |
3402922392 ps |
| T120 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2831869671 |
|
|
Aug 14 06:06:10 PM PDT 24 |
Aug 14 06:17:55 PM PDT 24 |
5241976351 ps |
| T121 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2621739608 |
|
|
Aug 14 06:06:39 PM PDT 24 |
Aug 14 06:19:58 PM PDT 24 |
4837687201 ps |
| T12 |
/workspace/coverage/default/2.chip_tap_straps_rma.2451885209 |
|
|
Aug 14 06:04:03 PM PDT 24 |
Aug 14 06:11:18 PM PDT 24 |
4501640124 ps |
| T26 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1587856144 |
|
|
Aug 14 05:47:11 PM PDT 24 |
Aug 14 09:48:11 PM PDT 24 |
79015748680 ps |
| T122 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.4240119786 |
|
|
Aug 14 05:57:12 PM PDT 24 |
Aug 14 06:03:53 PM PDT 24 |
4124669832 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.83993776 |
|
|
Aug 14 05:51:41 PM PDT 24 |
Aug 14 06:00:03 PM PDT 24 |
4678468679 ps |
| T90 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.731134528 |
|
|
Aug 14 05:57:29 PM PDT 24 |
Aug 14 05:59:19 PM PDT 24 |
2453411273 ps |
| T123 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250016360 |
|
|
Aug 14 06:17:25 PM PDT 24 |
Aug 14 06:24:18 PM PDT 24 |
3554265560 ps |
| T299 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2197540592 |
|
|
Aug 14 05:54:31 PM PDT 24 |
Aug 14 06:09:22 PM PDT 24 |
3910968724 ps |
| T130 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2692196951 |
|
|
Aug 14 06:06:24 PM PDT 24 |
Aug 14 06:15:41 PM PDT 24 |
4702677960 ps |
| T556 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3368157383 |
|
|
Aug 14 05:54:36 PM PDT 24 |
Aug 14 06:00:04 PM PDT 24 |
3359674760 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.255495353 |
|
|
Aug 14 05:55:36 PM PDT 24 |
Aug 14 06:19:51 PM PDT 24 |
8447787268 ps |
| T18 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.508484694 |
|
|
Aug 14 06:15:39 PM PDT 24 |
Aug 14 06:24:42 PM PDT 24 |
3349160472 ps |
| T182 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.106116581 |
|
|
Aug 14 05:52:14 PM PDT 24 |
Aug 14 05:57:08 PM PDT 24 |
3274557218 ps |
| T69 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.797425561 |
|
|
Aug 14 05:55:18 PM PDT 24 |
Aug 14 06:59:43 PM PDT 24 |
15108823412 ps |
| T239 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3439195794 |
|
|
Aug 14 06:11:38 PM PDT 24 |
Aug 14 06:18:59 PM PDT 24 |
4139039224 ps |
| T142 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1911045134 |
|
|
Aug 14 06:05:02 PM PDT 24 |
Aug 14 06:20:53 PM PDT 24 |
9063649936 ps |
| T172 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3103735355 |
|
|
Aug 14 06:12:57 PM PDT 24 |
Aug 14 06:23:55 PM PDT 24 |
4727161684 ps |
| T219 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.577503505 |
|
|
Aug 14 05:57:25 PM PDT 24 |
Aug 14 06:03:08 PM PDT 24 |
3750812430 ps |
| T128 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.496831129 |
|
|
Aug 14 05:57:03 PM PDT 24 |
Aug 14 06:19:22 PM PDT 24 |
8036448995 ps |
| T310 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4112563149 |
|
|
Aug 14 06:15:20 PM PDT 24 |
Aug 14 06:22:47 PM PDT 24 |
4032397550 ps |
| T127 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1991199721 |
|
|
Aug 14 05:51:41 PM PDT 24 |
Aug 14 06:10:34 PM PDT 24 |
7855386970 ps |
| T228 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1471092548 |
|
|
Aug 14 06:16:00 PM PDT 24 |
Aug 14 06:21:18 PM PDT 24 |
4298114250 ps |
| T19 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1902749014 |
|
|
Aug 14 06:03:10 PM PDT 24 |
Aug 14 06:09:51 PM PDT 24 |
3342222451 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3104693398 |
|
|
Aug 14 05:56:00 PM PDT 24 |
Aug 14 05:59:41 PM PDT 24 |
2513863064 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1684339560 |
|
|
Aug 14 05:58:03 PM PDT 24 |
Aug 14 06:05:58 PM PDT 24 |
6262322680 ps |
| T91 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.1697031067 |
|
|
Aug 14 05:50:00 PM PDT 24 |
Aug 14 05:51:50 PM PDT 24 |
2702573846 ps |
| T209 |
/workspace/coverage/default/0.chip_sival_flash_info_access.900626031 |
|
|
Aug 14 05:50:29 PM PDT 24 |
Aug 14 05:55:34 PM PDT 24 |
2404605496 ps |
| T274 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3424700763 |
|
|
Aug 14 06:00:56 PM PDT 24 |
Aug 14 06:24:49 PM PDT 24 |
10318227047 ps |
| T376 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.438382265 |
|
|
Aug 14 06:16:57 PM PDT 24 |
Aug 14 06:22:57 PM PDT 24 |
3423491712 ps |
| T515 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3977709996 |
|
|
Aug 14 06:14:45 PM PDT 24 |
Aug 14 06:21:40 PM PDT 24 |
3408776886 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2030488802 |
|
|
Aug 14 06:05:25 PM PDT 24 |
Aug 14 06:08:02 PM PDT 24 |
2657200432 ps |
| T27 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1404013861 |
|
|
Aug 14 05:55:40 PM PDT 24 |
Aug 14 06:30:13 PM PDT 24 |
21758833252 ps |
| T259 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1844381192 |
|
|
Aug 14 05:51:35 PM PDT 24 |
Aug 14 05:54:18 PM PDT 24 |
2302110592 ps |
| T240 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3667595384 |
|
|
Aug 14 06:15:17 PM PDT 24 |
Aug 14 06:22:53 PM PDT 24 |
3509973194 ps |
| T70 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.460550312 |
|
|
Aug 14 06:09:14 PM PDT 24 |
Aug 14 06:17:42 PM PDT 24 |
4902149177 ps |
| T36 |
/workspace/coverage/default/2.chip_sw_gpio.3555775949 |
|
|
Aug 14 05:58:16 PM PDT 24 |
Aug 14 06:06:16 PM PDT 24 |
3799328232 ps |
| T71 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3335819945 |
|
|
Aug 14 05:49:16 PM PDT 24 |
Aug 14 05:54:53 PM PDT 24 |
3376427242 ps |
| T173 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1626136336 |
|
|
Aug 14 06:16:15 PM PDT 24 |
Aug 14 06:25:55 PM PDT 24 |
5580684500 ps |
| T349 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1035766392 |
|
|
Aug 14 06:14:18 PM PDT 24 |
Aug 14 06:23:14 PM PDT 24 |
5062127344 ps |
| T181 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2996459309 |
|
|
Aug 14 05:54:43 PM PDT 24 |
Aug 14 05:59:36 PM PDT 24 |
3005629300 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3125568848 |
|
|
Aug 14 05:47:48 PM PDT 24 |
Aug 14 05:55:53 PM PDT 24 |
4602156776 ps |
| T13 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.267356975 |
|
|
Aug 14 05:54:14 PM PDT 24 |
Aug 14 06:00:12 PM PDT 24 |
4066048302 ps |
| T316 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.1530196012 |
|
|
Aug 14 05:49:34 PM PDT 24 |
Aug 14 05:53:10 PM PDT 24 |
3097590356 ps |
| T183 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1054602890 |
|
|
Aug 14 06:05:07 PM PDT 24 |
Aug 14 06:22:03 PM PDT 24 |
6744376100 ps |
| T131 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.520808838 |
|
|
Aug 14 06:06:25 PM PDT 24 |
Aug 14 06:23:31 PM PDT 24 |
4655394850 ps |
| T163 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3879276493 |
|
|
Aug 14 05:48:25 PM PDT 24 |
Aug 14 06:09:05 PM PDT 24 |
10581496860 ps |
| T387 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.1245508339 |
|
|
Aug 14 05:56:45 PM PDT 24 |
Aug 14 06:51:20 PM PDT 24 |
15294884101 ps |
| T178 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4029103526 |
|
|
Aug 14 05:51:35 PM PDT 24 |
Aug 14 06:00:50 PM PDT 24 |
5528372098 ps |
| T328 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.4131529830 |
|
|
Aug 14 06:17:36 PM PDT 24 |
Aug 14 06:25:28 PM PDT 24 |
6213114300 ps |
| T350 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2338664184 |
|
|
Aug 14 06:11:01 PM PDT 24 |
Aug 14 06:21:18 PM PDT 24 |
5146162600 ps |
| T258 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.647915258 |
|
|
Aug 14 06:09:35 PM PDT 24 |
Aug 14 06:19:54 PM PDT 24 |
5595564160 ps |
| T229 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2736924649 |
|
|
Aug 14 05:52:30 PM PDT 24 |
Aug 14 06:19:11 PM PDT 24 |
6716269260 ps |
| T275 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2689233553 |
|
|
Aug 14 06:00:50 PM PDT 24 |
Aug 14 06:29:58 PM PDT 24 |
15662931895 ps |
| T236 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3320299142 |
|
|
Aug 14 05:49:47 PM PDT 24 |
Aug 14 06:01:31 PM PDT 24 |
4699575312 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.572101036 |
|
|
Aug 14 05:51:02 PM PDT 24 |
Aug 14 06:00:57 PM PDT 24 |
7376354268 ps |
| T329 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2403280703 |
|
|
Aug 14 06:03:24 PM PDT 24 |
Aug 14 07:08:40 PM PDT 24 |
16253286456 ps |
| T557 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.30966058 |
|
|
Aug 14 05:59:54 PM PDT 24 |
Aug 14 06:19:30 PM PDT 24 |
7299599990 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_aes_enc.2916048157 |
|
|
Aug 14 05:53:45 PM PDT 24 |
Aug 14 05:56:58 PM PDT 24 |
2421282628 ps |
| T6 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2825779027 |
|
|
Aug 14 06:05:22 PM PDT 24 |
Aug 14 06:12:34 PM PDT 24 |
3919104948 ps |
| T31 |
/workspace/coverage/default/0.chip_sw_power_virus.1208068063 |
|
|
Aug 14 05:58:07 PM PDT 24 |
Aug 14 06:22:47 PM PDT 24 |
5704134356 ps |
| T277 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.574374072 |
|
|
Aug 14 06:14:53 PM PDT 24 |
Aug 14 06:27:28 PM PDT 24 |
6003448724 ps |
| T430 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1622058237 |
|
|
Aug 14 05:57:46 PM PDT 24 |
Aug 14 06:02:58 PM PDT 24 |
2912962040 ps |
| T431 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.338953215 |
|
|
Aug 14 06:07:47 PM PDT 24 |
Aug 14 06:12:17 PM PDT 24 |
3041935512 ps |
| T352 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1334931987 |
|
|
Aug 14 05:51:56 PM PDT 24 |
Aug 14 06:04:18 PM PDT 24 |
4716663288 ps |
| T325 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1882803527 |
|
|
Aug 14 06:12:12 PM PDT 24 |
Aug 14 06:21:30 PM PDT 24 |
5042034808 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3074878202 |
|
|
Aug 14 05:49:09 PM PDT 24 |
Aug 14 06:45:28 PM PDT 24 |
18596151705 ps |
| T244 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2984576844 |
|
|
Aug 14 05:52:50 PM PDT 24 |
Aug 14 05:58:11 PM PDT 24 |
2946338322 ps |
| T326 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3202699615 |
|
|
Aug 14 06:10:35 PM PDT 24 |
Aug 14 06:19:35 PM PDT 24 |
4611501774 ps |
| T359 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1975146024 |
|
|
Aug 14 06:02:23 PM PDT 24 |
Aug 14 06:19:34 PM PDT 24 |
5784939600 ps |
| T336 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.2713058972 |
|
|
Aug 14 05:53:33 PM PDT 24 |
Aug 14 06:50:17 PM PDT 24 |
15798505548 ps |
| T129 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.750554258 |
|
|
Aug 14 05:55:59 PM PDT 24 |
Aug 14 06:04:18 PM PDT 24 |
3865277442 ps |
| T96 |
/workspace/coverage/default/0.chip_tap_straps_prod.3515788905 |
|
|
Aug 14 05:51:42 PM PDT 24 |
Aug 14 06:07:22 PM PDT 24 |
8508754718 ps |
| T401 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2298089335 |
|
|
Aug 14 06:13:18 PM PDT 24 |
Aug 14 06:20:42 PM PDT 24 |
4409569182 ps |
| T20 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.4091512340 |
|
|
Aug 14 06:15:20 PM PDT 24 |
Aug 14 06:25:16 PM PDT 24 |
5080631236 ps |
| T157 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238938059 |
|
|
Aug 14 06:11:19 PM PDT 24 |
Aug 14 06:19:29 PM PDT 24 |
3898879060 ps |
| T143 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2150440901 |
|
|
Aug 14 05:52:46 PM PDT 24 |
Aug 14 05:59:53 PM PDT 24 |
4599644680 ps |
| T132 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2497712740 |
|
|
Aug 14 06:06:22 PM PDT 24 |
Aug 14 06:27:38 PM PDT 24 |
5887333160 ps |
| T558 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3251514393 |
|
|
Aug 14 05:54:03 PM PDT 24 |
Aug 14 05:58:57 PM PDT 24 |
3318715180 ps |
| T559 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.595510471 |
|
|
Aug 14 05:52:13 PM PDT 24 |
Aug 14 06:20:55 PM PDT 24 |
7643176104 ps |
| T560 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2449893406 |
|
|
Aug 14 06:04:30 PM PDT 24 |
Aug 14 06:16:15 PM PDT 24 |
4732018472 ps |
| T7 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3170726790 |
|
|
Aug 14 06:06:12 PM PDT 24 |
Aug 14 06:14:01 PM PDT 24 |
3978529636 ps |
| T153 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2095954423 |
|
|
Aug 14 06:10:12 PM PDT 24 |
Aug 14 06:20:51 PM PDT 24 |
4468651730 ps |
| T388 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4117052021 |
|
|
Aug 14 05:49:55 PM PDT 24 |
Aug 14 05:58:00 PM PDT 24 |
5338615990 ps |
| T374 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1580324880 |
|
|
Aug 14 05:50:43 PM PDT 24 |
Aug 14 06:19:40 PM PDT 24 |
12713745956 ps |
| T21 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.226744497 |
|
|
Aug 14 05:51:47 PM PDT 24 |
Aug 14 05:57:25 PM PDT 24 |
3157302665 ps |
| T561 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.365613142 |
|
|
Aug 14 06:09:19 PM PDT 24 |
Aug 14 06:14:28 PM PDT 24 |
3327219590 ps |
| T562 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3962042993 |
|
|
Aug 14 06:04:52 PM PDT 24 |
Aug 14 06:14:58 PM PDT 24 |
4736759500 ps |
| T563 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.644592039 |
|
|
Aug 14 06:05:25 PM PDT 24 |
Aug 14 06:32:47 PM PDT 24 |
7747478936 ps |
| T22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.823215803 |
|
|
Aug 14 05:51:10 PM PDT 24 |
Aug 14 06:19:12 PM PDT 24 |
13323265352 ps |
| T265 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2611177058 |
|
|
Aug 14 05:55:06 PM PDT 24 |
Aug 14 07:28:23 PM PDT 24 |
18156077246 ps |
| T102 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.1749419697 |
|
|
Aug 14 05:47:48 PM PDT 24 |
Aug 14 05:51:08 PM PDT 24 |
2431639022 ps |
| T389 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3914245332 |
|
|
Aug 14 05:54:21 PM PDT 24 |
Aug 14 07:02:17 PM PDT 24 |
14822768788 ps |
| T45 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2271130879 |
|
|
Aug 14 05:58:33 PM PDT 24 |
Aug 14 06:04:13 PM PDT 24 |
3674794200 ps |
| T10 |
/workspace/coverage/default/0.rom_raw_unlock.3121771732 |
|
|
Aug 14 05:48:48 PM PDT 24 |
Aug 14 05:53:42 PM PDT 24 |
3818331004 ps |
| T175 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2868217354 |
|
|
Aug 14 05:54:45 PM PDT 24 |
Aug 14 06:22:27 PM PDT 24 |
14366776328 ps |
| T412 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.545796706 |
|
|
Aug 14 06:19:10 PM PDT 24 |
Aug 14 06:26:21 PM PDT 24 |
4366267422 ps |
| T313 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.611633247 |
|
|
Aug 14 06:12:15 PM PDT 24 |
Aug 14 06:40:13 PM PDT 24 |
8261253760 ps |
| T413 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1116822143 |
|
|
Aug 14 06:04:46 PM PDT 24 |
Aug 14 06:09:39 PM PDT 24 |
2968257459 ps |
| T133 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.658330892 |
|
|
Aug 14 05:56:28 PM PDT 24 |
Aug 14 06:06:52 PM PDT 24 |
3487557754 ps |
| T414 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.196821130 |
|
|
Aug 14 05:48:25 PM PDT 24 |
Aug 14 05:54:43 PM PDT 24 |
3302923919 ps |
| T415 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1561397918 |
|
|
Aug 14 05:49:28 PM PDT 24 |
Aug 14 06:01:32 PM PDT 24 |
5374023304 ps |
| T276 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2895359716 |
|
|
Aug 14 06:08:56 PM PDT 24 |
Aug 14 07:50:44 PM PDT 24 |
29482292880 ps |
| T448 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.235544124 |
|
|
Aug 14 06:11:42 PM PDT 24 |
Aug 14 06:18:28 PM PDT 24 |
4340940564 ps |
| T218 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3688431678 |
|
|
Aug 14 05:53:09 PM PDT 24 |
Aug 14 06:04:16 PM PDT 24 |
6645586056 ps |
| T564 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1045518089 |
|
|
Aug 14 06:00:40 PM PDT 24 |
Aug 14 06:10:28 PM PDT 24 |
5760037421 ps |
| T322 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3154300869 |
|
|
Aug 14 06:02:20 PM PDT 24 |
Aug 14 06:15:55 PM PDT 24 |
4357146110 ps |
| T565 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1795667865 |
|
|
Aug 14 05:47:41 PM PDT 24 |
Aug 14 06:09:48 PM PDT 24 |
6053003162 ps |
| T278 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1564262822 |
|
|
Aug 14 06:16:38 PM PDT 24 |
Aug 14 06:26:18 PM PDT 24 |
4758761416 ps |
| T217 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.618828101 |
|
|
Aug 14 05:48:28 PM PDT 24 |
Aug 14 05:53:31 PM PDT 24 |
3439552050 ps |
| T315 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3553744870 |
|
|
Aug 14 05:47:02 PM PDT 24 |
Aug 14 05:58:39 PM PDT 24 |
4418322862 ps |
| T58 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.117993546 |
|
|
Aug 14 05:51:41 PM PDT 24 |
Aug 14 05:57:11 PM PDT 24 |
3700442271 ps |
| T373 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2195189802 |
|
|
Aug 14 06:16:19 PM PDT 24 |
Aug 14 06:26:23 PM PDT 24 |
4282243160 ps |
| T191 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2593248528 |
|
|
Aug 14 05:47:48 PM PDT 24 |
Aug 14 05:54:36 PM PDT 24 |
5077620669 ps |
| T529 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1310006139 |
|
|
Aug 14 06:14:54 PM PDT 24 |
Aug 14 06:23:47 PM PDT 24 |
4984455694 ps |
| T566 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2843187963 |
|
|
Aug 14 05:51:53 PM PDT 24 |
Aug 14 05:58:08 PM PDT 24 |
4675782294 ps |
| T344 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3315377686 |
|
|
Aug 14 05:55:51 PM PDT 24 |
Aug 14 05:58:42 PM PDT 24 |
2664311880 ps |
| T567 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3170119904 |
|
|
Aug 14 05:59:45 PM PDT 24 |
Aug 14 06:05:00 PM PDT 24 |
3108732071 ps |
| T478 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1335042735 |
|
|
Aug 14 06:13:30 PM PDT 24 |
Aug 14 06:21:58 PM PDT 24 |
5579683538 ps |
| T212 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2973587325 |
|
|
Aug 14 05:51:35 PM PDT 24 |
Aug 14 05:59:39 PM PDT 24 |
6022925743 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3070377154 |
|
|
Aug 14 05:59:20 PM PDT 24 |
Aug 14 07:34:19 PM PDT 24 |
50158302457 ps |
| T484 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3558241492 |
|
|
Aug 14 06:09:18 PM PDT 24 |
Aug 14 06:20:45 PM PDT 24 |
6200983142 ps |
| T346 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2157673183 |
|
|
Aug 14 06:12:23 PM PDT 24 |
Aug 14 06:19:22 PM PDT 24 |
4021760520 ps |
| T216 |
/workspace/coverage/default/0.chip_sw_flash_init.209174306 |
|
|
Aug 14 05:47:39 PM PDT 24 |
Aug 14 06:22:43 PM PDT 24 |
20428292805 ps |
| T39 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.4152755177 |
|
|
Aug 14 05:49:31 PM PDT 24 |
Aug 14 07:33:24 PM PDT 24 |
31644181968 ps |
| T167 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1434217752 |
|
|
Aug 14 06:03:47 PM PDT 24 |
Aug 14 06:13:54 PM PDT 24 |
8949516554 ps |
| T154 |
/workspace/coverage/default/0.chip_sw_power_idle_load.3561125195 |
|
|
Aug 14 05:52:05 PM PDT 24 |
Aug 14 06:03:14 PM PDT 24 |
4733308218 ps |
| T11 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3347157429 |
|
|
Aug 14 05:55:29 PM PDT 24 |
Aug 14 06:02:27 PM PDT 24 |
5158148040 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.902988745 |
|
|
Aug 14 05:51:01 PM PDT 24 |
Aug 14 07:25:39 PM PDT 24 |
47088046834 ps |
| T474 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.883757344 |
|
|
Aug 14 06:16:48 PM PDT 24 |
Aug 14 06:26:37 PM PDT 24 |
5769788296 ps |
| T40 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.3486534668 |
|
|
Aug 14 05:51:41 PM PDT 24 |
Aug 14 06:42:12 PM PDT 24 |
11850347540 ps |
| T176 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2135185776 |
|
|
Aug 14 05:56:10 PM PDT 24 |
Aug 14 06:22:02 PM PDT 24 |
10941579720 ps |
| T14 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.135295439 |
|
|
Aug 14 05:50:10 PM PDT 24 |
Aug 14 06:23:51 PM PDT 24 |
24947533668 ps |
| T481 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3428284935 |
|
|
Aug 14 06:13:23 PM PDT 24 |
Aug 14 06:25:00 PM PDT 24 |
6023664696 ps |
| T286 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2285678844 |
|
|
Aug 14 05:53:50 PM PDT 24 |
Aug 14 05:55:36 PM PDT 24 |
2224927348 ps |
| T403 |
/workspace/coverage/default/2.chip_sw_edn_kat.3427894 |
|
|
Aug 14 06:04:00 PM PDT 24 |
Aug 14 06:16:41 PM PDT 24 |
3651736030 ps |
| T390 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2523020504 |
|
|
Aug 14 05:55:43 PM PDT 24 |
Aug 14 07:00:43 PM PDT 24 |
16003079805 ps |
| T184 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1035591937 |
|
|
Aug 14 05:58:57 PM PDT 24 |
Aug 14 06:05:38 PM PDT 24 |
5181356944 ps |
| T536 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2618606315 |
|
|
Aug 14 06:17:08 PM PDT 24 |
Aug 14 06:23:11 PM PDT 24 |
3392159800 ps |
| T41 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2178362692 |
|
|
Aug 14 05:48:20 PM PDT 24 |
Aug 14 05:53:48 PM PDT 24 |
2994273076 ps |
| T568 |
/workspace/coverage/default/2.chip_sw_aes_enc.2728768814 |
|
|
Aug 14 06:01:41 PM PDT 24 |
Aug 14 06:07:42 PM PDT 24 |
3721347200 ps |
| T460 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1636503224 |
|
|
Aug 14 06:14:45 PM PDT 24 |
Aug 14 06:24:46 PM PDT 24 |
5594886736 ps |
| T368 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1056202695 |
|
|
Aug 14 05:56:28 PM PDT 24 |
Aug 14 06:07:05 PM PDT 24 |
4804005218 ps |
| T64 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2197818103 |
|
|
Aug 14 05:57:11 PM PDT 24 |
Aug 14 06:50:52 PM PDT 24 |
14487891366 ps |
| T569 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2884691036 |
|
|
Aug 14 05:51:34 PM PDT 24 |
Aug 14 06:01:32 PM PDT 24 |
5629949464 ps |
| T570 |
/workspace/coverage/default/4.chip_tap_straps_dev.3415083277 |
|
|
Aug 14 06:09:19 PM PDT 24 |
Aug 14 06:12:44 PM PDT 24 |
3635920701 ps |
| T571 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1854661731 |
|
|
Aug 14 05:50:30 PM PDT 24 |
Aug 14 05:56:19 PM PDT 24 |
2742150860 ps |
| T572 |
/workspace/coverage/default/1.chip_sw_aes_idle.1499040954 |
|
|
Aug 14 05:55:54 PM PDT 24 |
Aug 14 05:59:12 PM PDT 24 |
2899464088 ps |
| T347 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1466048274 |
|
|
Aug 14 06:07:02 PM PDT 24 |
Aug 14 06:15:56 PM PDT 24 |
3874416340 ps |
| T330 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4204804100 |
|
|
Aug 14 06:12:52 PM PDT 24 |
Aug 14 06:18:18 PM PDT 24 |
4192794580 ps |
| T272 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1079711451 |
|
|
Aug 14 05:57:19 PM PDT 24 |
Aug 14 06:02:58 PM PDT 24 |
3199398390 ps |
| T573 |
/workspace/coverage/default/0.chip_sw_aes_enc.2481708327 |
|
|
Aug 14 05:47:53 PM PDT 24 |
Aug 14 05:51:58 PM PDT 24 |
3078758648 ps |
| T353 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2619978890 |
|
|
Aug 14 06:17:12 PM PDT 24 |
Aug 14 06:25:53 PM PDT 24 |
5541160844 ps |
| T287 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3263838522 |
|
|
Aug 14 05:54:49 PM PDT 24 |
Aug 14 05:56:49 PM PDT 24 |
2603247600 ps |
| T188 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3129832346 |
|
|
Aug 14 05:52:09 PM PDT 24 |
Aug 14 06:06:34 PM PDT 24 |
6527319984 ps |
| T574 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.70306758 |
|
|
Aug 14 05:49:39 PM PDT 24 |
Aug 14 06:32:11 PM PDT 24 |
27991579115 ps |
| T575 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3714815314 |
|
|
Aug 14 05:53:34 PM PDT 24 |
Aug 14 06:05:05 PM PDT 24 |
5162249496 ps |
| T192 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2580928431 |
|
|
Aug 14 05:49:04 PM PDT 24 |
Aug 14 06:10:41 PM PDT 24 |
6768073520 ps |
| T530 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.2819537970 |
|
|
Aug 14 06:10:30 PM PDT 24 |
Aug 14 06:20:21 PM PDT 24 |
5046563598 ps |
| T279 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3192806884 |
|
|
Aug 14 05:52:08 PM PDT 24 |
Aug 14 06:04:50 PM PDT 24 |
6449774880 ps |
| T237 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2613472561 |
|
|
Aug 14 05:51:34 PM PDT 24 |
Aug 14 06:02:35 PM PDT 24 |
4348219254 ps |
| T197 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.688553527 |
|
|
Aug 14 05:51:48 PM PDT 24 |
Aug 14 06:01:25 PM PDT 24 |
4462072234 ps |
| T65 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2650309838 |
|
|
Aug 14 05:55:29 PM PDT 24 |
Aug 14 06:36:28 PM PDT 24 |
11161728473 ps |
| T95 |
/workspace/coverage/default/3.chip_tap_straps_rma.1519312073 |
|
|
Aug 14 06:07:05 PM PDT 24 |
Aug 14 06:11:18 PM PDT 24 |
4044264381 ps |
| T576 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1804841041 |
|
|
Aug 14 05:51:44 PM PDT 24 |
Aug 14 05:56:11 PM PDT 24 |
2664388960 ps |
| T531 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2346612989 |
|
|
Aug 14 06:12:24 PM PDT 24 |
Aug 14 06:22:08 PM PDT 24 |
5039034660 ps |
| T378 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.598648483 |
|
|
Aug 14 06:13:43 PM PDT 24 |
Aug 14 06:22:33 PM PDT 24 |
4055108482 ps |
| T402 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.410553481 |
|
|
Aug 14 06:10:43 PM PDT 24 |
Aug 14 07:39:18 PM PDT 24 |
21348139304 ps |
| T168 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.2482923758 |
|
|
Aug 14 06:04:05 PM PDT 24 |
Aug 14 06:08:30 PM PDT 24 |
2707852472 ps |
| T366 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1266854703 |
|
|
Aug 14 05:48:43 PM PDT 24 |
Aug 14 05:58:29 PM PDT 24 |
3758448382 ps |
| T220 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2638231273 |
|
|
Aug 14 05:51:06 PM PDT 24 |
Aug 14 05:54:52 PM PDT 24 |
2772548143 ps |
| T280 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4111204684 |
|
|
Aug 14 05:49:24 PM PDT 24 |
Aug 14 06:05:41 PM PDT 24 |
7859966160 ps |
| T405 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.669438021 |
|
|
Aug 14 05:53:34 PM PDT 24 |
Aug 14 05:58:23 PM PDT 24 |
2829894048 ps |
| T82 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1065183361 |
|
|
Aug 14 05:46:57 PM PDT 24 |
Aug 14 05:56:13 PM PDT 24 |
5877351900 ps |
| T406 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2130763439 |
|
|
Aug 14 05:58:58 PM PDT 24 |
Aug 14 06:19:47 PM PDT 24 |
8273463208 ps |
| T407 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.4236114838 |
|
|
Aug 14 06:15:40 PM PDT 24 |
Aug 14 06:26:24 PM PDT 24 |
4889759386 ps |
| T288 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.1510844559 |
|
|
Aug 14 06:06:57 PM PDT 24 |
Aug 14 06:08:53 PM PDT 24 |
2342765112 ps |
| T416 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1939461744 |
|
|
Aug 14 06:10:04 PM PDT 24 |
Aug 14 06:16:52 PM PDT 24 |
3414462840 ps |
| T206 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1995875712 |
|
|
Aug 14 05:52:41 PM PDT 24 |
Aug 14 06:02:34 PM PDT 24 |
5112575590 ps |
| T66 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1719370097 |
|
|
Aug 14 05:56:04 PM PDT 24 |
Aug 14 06:48:20 PM PDT 24 |
13576957382 ps |
| T169 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3683692598 |
|
|
Aug 14 06:09:59 PM PDT 24 |
Aug 14 06:19:39 PM PDT 24 |
4757379840 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_flash_init.3503280728 |
|
|
Aug 14 05:49:00 PM PDT 24 |
Aug 14 06:29:57 PM PDT 24 |
19362451290 ps |
| T293 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3025246182 |
|
|
Aug 14 05:56:43 PM PDT 24 |
Aug 14 06:07:02 PM PDT 24 |
4227988400 ps |
| T245 |
/workspace/coverage/default/0.chip_sw_hmac_enc.1692110415 |
|
|
Aug 14 05:53:14 PM PDT 24 |
Aug 14 05:58:43 PM PDT 24 |
3235811910 ps |
| T577 |
/workspace/coverage/default/0.chip_sw_aes_idle.2184707182 |
|
|
Aug 14 05:49:39 PM PDT 24 |
Aug 14 05:53:59 PM PDT 24 |
2370001118 ps |
| T377 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.720807150 |
|
|
Aug 14 06:01:26 PM PDT 24 |
Aug 14 06:56:22 PM PDT 24 |
23486224541 ps |
| T461 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1365941886 |
|
|
Aug 14 06:15:21 PM PDT 24 |
Aug 14 06:22:45 PM PDT 24 |
4048136126 ps |
| T578 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.313935292 |
|
|
Aug 14 06:02:41 PM PDT 24 |
Aug 14 06:07:25 PM PDT 24 |
2444234174 ps |
| T579 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.274276076 |
|
|
Aug 14 06:04:03 PM PDT 24 |
Aug 14 06:54:26 PM PDT 24 |
31665080325 ps |
| T337 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1302333054 |
|
|
Aug 14 05:53:31 PM PDT 24 |
Aug 14 07:28:25 PM PDT 24 |
46551097052 ps |
| T580 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3357801106 |
|
|
Aug 14 06:07:35 PM PDT 24 |
Aug 14 06:14:32 PM PDT 24 |
6064128932 ps |
| T233 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.978037554 |
|
|
Aug 14 05:49:36 PM PDT 24 |
Aug 14 06:11:28 PM PDT 24 |
6162038672 ps |
| T28 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1502685443 |
|
|
Aug 14 05:50:44 PM PDT 24 |
Aug 14 05:56:19 PM PDT 24 |
3607051188 ps |
| T581 |
/workspace/coverage/default/0.rom_e2e_self_hash.3316653571 |
|
|
Aug 14 05:54:14 PM PDT 24 |
Aug 14 07:23:04 PM PDT 24 |
25128116084 ps |
| T472 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4199145912 |
|
|
Aug 14 06:16:09 PM PDT 24 |
Aug 14 06:26:00 PM PDT 24 |
5248439896 ps |
| T582 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1167350573 |
|
|
Aug 14 05:54:22 PM PDT 24 |
Aug 14 06:24:51 PM PDT 24 |
15591220396 ps |
| T483 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2000308426 |
|
|
Aug 14 06:15:16 PM PDT 24 |
Aug 14 06:22:34 PM PDT 24 |
4379109598 ps |
| T125 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3945403307 |
|
|
Aug 14 05:51:12 PM PDT 24 |
Aug 14 06:00:09 PM PDT 24 |
7348040644 ps |
| T8 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.566871522 |
|
|
Aug 14 05:51:50 PM PDT 24 |
Aug 14 05:59:31 PM PDT 24 |
4339776790 ps |
| T583 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2332640500 |
|
|
Aug 14 06:10:36 PM PDT 24 |
Aug 14 06:20:23 PM PDT 24 |
6877775315 ps |
| T360 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2429584227 |
|
|
Aug 14 06:08:46 PM PDT 24 |
Aug 14 06:18:15 PM PDT 24 |
4243547990 ps |
| T584 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.3372406833 |
|
|
Aug 14 05:55:06 PM PDT 24 |
Aug 14 06:01:04 PM PDT 24 |
3313456416 ps |
| T473 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2106799875 |
|
|
Aug 14 05:52:12 PM PDT 24 |
Aug 14 06:10:05 PM PDT 24 |
8125366424 ps |
| T224 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4210568200 |
|
|
Aug 14 06:04:32 PM PDT 24 |
Aug 14 06:15:45 PM PDT 24 |
4378944052 ps |
| T94 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2433451232 |
|
|
Aug 14 05:49:54 PM PDT 24 |
Aug 14 05:53:12 PM PDT 24 |
2891566972 ps |
| T273 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.2942960191 |
|
|
Aug 14 05:54:05 PM PDT 24 |
Aug 14 05:58:16 PM PDT 24 |
2837609338 ps |
| T32 |
/workspace/coverage/default/2.chip_sw_power_virus.1235249792 |
|
|
Aug 14 06:13:58 PM PDT 24 |
Aug 14 06:37:59 PM PDT 24 |
5612190600 ps |
| T585 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2358822811 |
|
|
Aug 14 06:12:24 PM PDT 24 |
Aug 14 06:55:55 PM PDT 24 |
11420974738 ps |
| T345 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3187960783 |
|
|
Aug 14 06:07:14 PM PDT 24 |
Aug 14 06:16:50 PM PDT 24 |
4448577266 ps |
| T586 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2683351716 |
|
|
Aug 14 05:48:13 PM PDT 24 |
Aug 14 05:54:20 PM PDT 24 |
3711948488 ps |
| T500 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.753399729 |
|
|
Aug 14 06:16:27 PM PDT 24 |
Aug 14 06:28:53 PM PDT 24 |
5481822660 ps |
| T370 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4265899017 |
|
|
Aug 14 06:11:22 PM PDT 24 |
Aug 14 06:49:29 PM PDT 24 |
12421889476 ps |
| T587 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3109830836 |
|
|
Aug 14 05:54:01 PM PDT 24 |
Aug 14 06:02:17 PM PDT 24 |
5903316120 ps |
| T588 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.3873841496 |
|
|
Aug 14 05:56:24 PM PDT 24 |
Aug 14 06:01:07 PM PDT 24 |
2745718458 ps |
| T589 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2897470249 |
|
|
Aug 14 05:52:44 PM PDT 24 |
Aug 14 06:03:03 PM PDT 24 |
4149617416 ps |
| T590 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.1674356564 |
|
|
Aug 14 05:47:35 PM PDT 24 |
Aug 14 05:52:05 PM PDT 24 |
3275370352 ps |
| T591 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2949642801 |
|
|
Aug 14 06:10:53 PM PDT 24 |
Aug 14 06:27:33 PM PDT 24 |
12330093143 ps |
| T261 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4238937363 |
|
|
Aug 14 05:53:57 PM PDT 24 |
Aug 14 06:04:16 PM PDT 24 |
5226015724 ps |
| T592 |
/workspace/coverage/default/1.chip_sw_hmac_enc.3359857288 |
|
|
Aug 14 05:54:12 PM PDT 24 |
Aug 14 05:59:17 PM PDT 24 |
3415179110 ps |
| T266 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.118738907 |
|
|
Aug 14 05:54:50 PM PDT 24 |
Aug 14 07:36:50 PM PDT 24 |
23892846092 ps |