Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.66 84.66

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_i2c0 84.48 84.48
tb.dut.top_earlgrey.u_i2c1 84.57 84.57
tb.dut.top_earlgrey.u_i2c2 84.57 84.57



Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.48 84.48


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.48 84.48


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.22 92.47 87.18 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.57 84.57


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.57 84.57


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.22 92.47 87.18 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.57 84.57


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.57 84.57


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.22 92.47 87.18 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 54 40 74.07
Total Bits 352 298 84.66
Total Bits 0->1 176 149 84.66
Total Bits 1->0 176 149 84.66

Ports 54 40 74.07
Port Bits 352 298 84.66
Port Bits 0->1 176 149 84.66
Port Bits 1->0 176 149 84.66

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T236,T31,T237 Yes T236,T31,T237 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T236,T31,T237 Yes T236,T31,T237 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T7,*T10,*T14 Yes T7,T10,T14 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T49,T50,T51 Yes T49,T50,T51 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T99,*T100,*T101 Yes T99,T100,T101 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T236,T31,T175 Yes T236,T31,T175 INPUT
tl_o.a_ready Yes Yes T236,T31,T175 Yes T236,T31,T175 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T236,T31,T237 Yes T236,T31,T237 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T236,T31,T175 Yes T236,T31,T175 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T175,T238,T100 Yes T236,T31,T175 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T236,T31,T175 Yes T236,T31,T175 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T100,*T236,*T31 Yes T100,T236,T31 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T175,T238,T100 Yes T236,T31,T175 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T236,*T31,*T237 Yes T236,T31,T237 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T236,T31,T175 Yes T236,T31,T175 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T239,T19,T240 Yes T239,T19,T240 INPUT
alert_rx_i[0].ping_n Yes Yes T19,T21,T22 Yes T19,T21,T22 INPUT
alert_rx_i[0].ping_p Yes Yes T19,T21,T22 Yes T19,T21,T22 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T239,T19,T240 Yes T239,T19,T240 OUTPUT
cio_scl_i Yes Yes T236,T31,T237 Yes T236,T31,T237 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T31,T237,T32 Yes T31,T237,T32 OUTPUT
cio_sda_i Yes Yes T236,T31,T237 Yes T236,T31,T237 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T236,T31,T237 Yes T236,T31,T237 OUTPUT
intr_fmt_threshold_o Yes Yes T237,T233,T241 Yes T237,T233,T241 OUTPUT
intr_rx_threshold_o Yes Yes T237,T233,T241 Yes T237,T233,T241 OUTPUT
intr_acq_threshold_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_rx_overflow_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_controller_halt_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_scl_interference_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_sda_interference_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_stretch_timeout_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_sda_unstable_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_cmd_complete_o Yes Yes T236,T237,T233 Yes T236,T237,T233 OUTPUT
intr_tx_stretch_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_tx_threshold_o Yes Yes T233,T100,T234 Yes T233,T100,T234 OUTPUT
intr_acq_stretch_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_unexp_stop_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_host_timeout_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0
TotalCoveredPercent
Totals 54 40 74.07
Total Bits 348 294 84.48
Total Bits 0->1 174 147 84.48
Total Bits 1->0 174 147 84.48

Ports 54 40 74.07
Port Bits 348 294 84.48
Port Bits 0->1 174 147 84.48
Port Bits 1->0 174 147 84.48

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T31,T233,T32 Yes T31,T233,T32 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T31,T233,T32 Yes T31,T233,T32 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T7,*T10,*T14 Yes T7,T10,T14 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T49,T50,T51 Yes T49,T50,T51 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T99,*T100,*T101 Yes T99,T100,T101 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T31,T175,T233 Yes T31,T175,T233 INPUT
tl_o.a_ready Yes Yes T31,T175,T233 Yes T31,T175,T233 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T31,T233,T32 Yes T31,T233,T32 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T31,T175,T233 Yes T31,T175,T233 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T175,T238,T100 Yes T31,T175,T233 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T31,T175,T233 Yes T31,T175,T233 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T100,*T31,*T175 Yes T100,T31,T175 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T175,T238,T100 Yes T31,T175,T233 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T31,*T233,*T32 Yes T31,T233,T32 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T31,T175,T233 Yes T31,T175,T233 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T239,T19,T21 Yes T239,T19,T21 INPUT
alert_rx_i[0].ping_n Yes Yes T19,T21,T22 Yes T21,T22,T23 INPUT
alert_rx_i[0].ping_p Yes Yes T21,T22,T23 Yes T19,T21,T22 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T239,T19,T21 Yes T239,T19,T21 OUTPUT
cio_scl_i Yes Yes T31,T32,T242 Yes T31,T32,T242 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T31,T32,T242 Yes T31,T32,T242 OUTPUT
cio_sda_i Yes Yes T31,T32,T242 Yes T31,T32,T242 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T31,T32,T242 Yes T31,T32,T242 OUTPUT
intr_fmt_threshold_o Yes Yes T233,T242,T243 Yes T233,T242,T243 OUTPUT
intr_rx_threshold_o Yes Yes T233,T242,T243 Yes T233,T242,T243 OUTPUT
intr_acq_threshold_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_rx_overflow_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_controller_halt_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_scl_interference_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_sda_interference_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_stretch_timeout_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_sda_unstable_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_cmd_complete_o Yes Yes T233,T242,T243 Yes T233,T242,T243 OUTPUT
intr_tx_stretch_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_tx_threshold_o Yes Yes T233,T100,T234 Yes T233,T100,T234 OUTPUT
intr_acq_stretch_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_unexp_stop_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_host_timeout_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1
TotalCoveredPercent
Totals 54 40 74.07
Total Bits 350 296 84.57
Total Bits 0->1 175 148 84.57
Total Bits 1->0 175 148 84.57

Ports 54 40 74.07
Port Bits 350 296 84.57
Port Bits 0->1 175 148 84.57
Port Bits 1->0 175 148 84.57

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T236,T31,T237 Yes T236,T31,T237 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T236,T31,T237 Yes T236,T31,T237 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T7,*T10,*T14 Yes T7,T10,T14 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T49,T50,T51 Yes T49,T50,T51 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T99,*T100,*T101 Yes T99,T100,T101 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T236,T31,T175 Yes T236,T31,T175 INPUT
tl_o.a_ready Yes Yes T236,T31,T175 Yes T236,T31,T175 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T236,T31,T237 Yes T236,T31,T237 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T236,T31,T175 Yes T236,T31,T175 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T175,T238,T100 Yes T236,T31,T175 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T236,T31,T175 Yes T236,T31,T175 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T100,*T236,*T31 Yes T100,T236,T31 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T175,T238,T100 Yes T236,T31,T175 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T236,*T31,*T237 Yes T236,T31,T237 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T236,T31,T175 Yes T236,T31,T175 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T19,T21,T22 Yes T19,T21,T22 INPUT
alert_rx_i[0].ping_n Yes Yes T19,T21,T22 Yes T19,T21,T22 INPUT
alert_rx_i[0].ping_p Yes Yes T19,T21,T22 Yes T19,T21,T22 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T19,T21,T22 Yes T19,T21,T22 OUTPUT
cio_scl_i Yes Yes T236,T31,T237 Yes T236,T31,T237 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T31,T237,T32 Yes T31,T237,T32 OUTPUT
cio_sda_i Yes Yes T236,T31,T237 Yes T236,T31,T237 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T236,T31,T237 Yes T236,T31,T237 OUTPUT
intr_fmt_threshold_o Yes Yes T237,T233,T100 Yes T237,T233,T100 OUTPUT
intr_rx_threshold_o Yes Yes T237,T233,T234 Yes T237,T233,T234 OUTPUT
intr_acq_threshold_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_rx_overflow_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_controller_halt_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_scl_interference_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_sda_interference_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_stretch_timeout_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_sda_unstable_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_cmd_complete_o Yes Yes T236,T237,T233 Yes T236,T237,T233 OUTPUT
intr_tx_stretch_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_tx_threshold_o Yes Yes T233,T100,T234 Yes T233,T100,T234 OUTPUT
intr_acq_stretch_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_unexp_stop_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_host_timeout_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2
TotalCoveredPercent
Totals 54 40 74.07
Total Bits 350 296 84.57
Total Bits 0->1 175 148 84.57
Total Bits 1->0 175 148 84.57

Ports 54 40 74.07
Port Bits 350 296 84.57
Port Bits 0->1 175 148 84.57
Port Bits 1->0 175 148 84.57

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T31,T233,T32 Yes T31,T233,T32 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T31,T233,T32 Yes T31,T233,T32 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T7,*T10,*T14 Yes T7,T10,T14 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T49,T50,T51 Yes T49,T50,T51 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T99,*T100,*T101 Yes T99,T100,T101 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T31,T175,T233 Yes T31,T175,T233 INPUT
tl_o.a_ready Yes Yes T31,T175,T233 Yes T31,T175,T233 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T31,T233,T32 Yes T31,T233,T32 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T31,T175,T233 Yes T31,T175,T233 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T175,T238,T100 Yes T31,T175,T233 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T31,T175,T233 Yes T31,T175,T233 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T100,*T31,*T175 Yes T100,T31,T175 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T175,T238,T100 Yes T31,T175,T233 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T31,*T233,*T32 Yes T31,T233,T32 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T31,T175,T233 Yes T31,T175,T233 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T19,T240,T21 Yes T19,T240,T21 INPUT
alert_rx_i[0].ping_n Yes Yes T19,T21,T22 Yes T19,T21,T22 INPUT
alert_rx_i[0].ping_p Yes Yes T19,T21,T22 Yes T19,T21,T22 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T19,T240,T21 Yes T19,T240,T21 OUTPUT
cio_scl_i Yes Yes T31,T32,T241 Yes T31,T32,T241 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T31,T32,T241 Yes T31,T32,T241 OUTPUT
cio_sda_i Yes Yes T31,T32,T241 Yes T31,T32,T241 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T31,T32,T241 Yes T31,T32,T241 OUTPUT
intr_fmt_threshold_o Yes Yes T233,T241,T114 Yes T233,T241,T114 OUTPUT
intr_rx_threshold_o Yes Yes T233,T241,T114 Yes T233,T241,T114 OUTPUT
intr_acq_threshold_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_rx_overflow_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_controller_halt_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_scl_interference_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_sda_interference_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_stretch_timeout_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_sda_unstable_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_cmd_complete_o Yes Yes T233,T241,T114 Yes T233,T241,T114 OUTPUT
intr_tx_stretch_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_tx_threshold_o Yes Yes T233,T100,T234 Yes T233,T100,T234 OUTPUT
intr_acq_stretch_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_unexp_stop_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT
intr_host_timeout_o Yes Yes T233,T234,T235 Yes T233,T234,T235 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%