Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.39			64.39

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_dm	64.39			64.39

---

Module Instance : tb.dut.top_earlgrey.u_rv_dm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.39			64.39

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.39			64.39

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	92.47		87.18			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	86	48	55.81
Total Bits	938	604	64.39
Total Bits 0->1	469	302	64.39
Total Bits 1->0	469	302	64.39

Ports	86	48	55.81
Port Bits	938	604	64.39
Port Bits 0->1	469	302	64.39
Port Bits 1->0	469	302	64.39

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
next_dm_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
otp_dis_rv_dm_late_debug_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T5	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
ndmreset_req_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
dmactive_o	Yes	Yes	T9,T10,T11	Yes	T12,T13,T9	OUTPUT
debug_req_o	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	OUTPUT
unavailable_i	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.d_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	No	No		No		INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	No	No		No		INPUT
regs_tl_d_i.a_user.instr_type[3:0]	No	No		No		INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_data[31:0]	No	No		No		INPUT
regs_tl_d_i.a_mask[3:0]	No	No		No		INPUT
regs_tl_d_i.a_address[3:0]	No	No		No		INPUT
regs_tl_d_i.a_address[20:4]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[21]	No	No		No		INPUT
regs_tl_d_i.a_address[23:22]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[24]	No	No		No		INPUT
regs_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[30]	No	No		No		INPUT
regs_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_source[5:0]	No	No		No		INPUT
regs_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_size[1:0]	No	No		No		INPUT
regs_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_opcode[2:0]	No	No		No		INPUT
regs_tl_d_i.a_valid	No	No		No		INPUT
regs_tl_d_o.a_ready	No	No		No		OUTPUT
regs_tl_d_o.d_error	No	No		No		OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
regs_tl_d_o.d_user.rsp_intg[6:0]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	No	No		No		OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[5:0]	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_size[1:0]	No	No		No		OUTPUT
regs_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_opcode[0]	No	No		No		OUTPUT
regs_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_valid	No	No		No		OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_address[1:0]	No	No		No		INPUT
mem_tl_d_i.a_address[11:2]	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_address[15:12]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_address[16]	Yes	Yes	*T7,*T14,*T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_address[31:17]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_source[4:0]	Yes	Yes	*T7,*T14,*T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_source[5]	No	No		No		INPUT
mem_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_size[0]	No	No		No		INPUT
mem_tl_d_i.a_size[1]	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
mem_tl_d_i.a_opcode[2]	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T5	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	OUTPUT
mem_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T7,*T14,*T15	Yes	T7,T14,T15	OUTPUT
mem_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	*T7,*T16,*T17	Yes	T7,T14,T15	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T5	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[4:0]	Yes	Yes	*T7,*T14,*T15	Yes	T7,T14,T15	OUTPUT
mem_tl_d_o.d_source[5]	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_size[0]	No	No		No		OUTPUT
mem_tl_d_o.d_size[1]	Yes	Yes	T7,T16,T17	Yes	T7,T14,T15	OUTPUT
mem_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T4,T5	OUTPUT
mem_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T7,T14,T15	Yes	T7,T14,T15	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	OUTPUT
sba_tl_h_o.a_source[5:0]	No	No		No		OUTPUT
sba_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_opcode[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	No	No		No		INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	INPUT
sba_tl_h_i.d_user.rsp_intg[1:0]	Yes	Yes	T12,T13,T10	Yes	T12,T13,T10	INPUT
sba_tl_h_i.d_user.rsp_intg[2]	No	No		No		INPUT
sba_tl_h_i.d_user.rsp_intg[5:3]	Yes	Yes	T12,T13,*T7	Yes	T12,T13,T7	INPUT
sba_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	INPUT
sba_tl_h_i.d_sink	No	No		No		INPUT
sba_tl_h_i.d_source[5:0]	No	No		No		INPUT
sba_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_size[0]	No	No		No		INPUT
sba_tl_h_i.d_size[1]	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	INPUT
sba_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_opcode[0]	Yes	Yes	*T12,*T13,*T7	Yes	T12,T13,T7	INPUT
sba_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_valid	Yes	Yes	T12,T13,T7	Yes	T12,T13,T7	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T19,T21,T22	Yes	T21,T22,T23	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T21,T22,T23	Yes	T19,T21,T22	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
jtag_i.tdi	Yes	Yes	T12,T13,T9	Yes	T12,T13,T9	INPUT
jtag_i.trst_n	Yes	Yes	T12,T13,T9	Yes	T12,T13,T9	INPUT
jtag_i.tms	Yes	Yes	T12,T13,T9	Yes	T12,T13,T9	INPUT
jtag_i.tck	Yes	Yes	T12,T13,T9	Yes	T12,T13,T9	INPUT
jtag_o.tdo_oe	Yes	Yes	T12,T13,T9	Yes	T12,T13,T9	OUTPUT
jtag_o.tdo	Yes	Yes	T12,T13,T9	Yes	T12,T13,T9	OUTPUT

*Tests covering at least one bit in the range