Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.82			83.82

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_usbdev	83.82			83.82

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Module Instance : tb.dut.top_earlgrey.u_usbdev

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.82			83.82

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.82			83.82

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	92.47		87.18			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

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Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	77	61	79.22
Total Bits	408	342	83.82
Total Bits 0->1	204	171	83.82
Total Bits 1->0	204	171	83.82

Ports	77	61	79.22
Port Bits	408	342	83.82
Port Bits 0->1	204	171	83.82
Port Bits 1->0	204	171	83.82

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T37,*T38	Yes	T4,T37,T38	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[11:2]	Yes	Yes	*T4,*T177,*T178	Yes	T4,T177,T178	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T37,*T38	Yes	T4,T37,T38	INPUT
tl_i.a_address[19:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T37,*T38	Yes	T4,T37,T38	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T101,*T4,*T37	Yes	T101,T4,T37	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T177,T178	Yes	T4,T177,T178	INPUT
tl_i.a_valid	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	INPUT
tl_o.a_ready	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T177,T178	Yes	T4,T177,T178	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T177,T178	Yes	T4,T177,T178	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T38,T177	Yes	T4,T37,T38	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T37,T38	Yes	T4,T38,T177	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T101,*T4,*T38	Yes	T101,T4,T37	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T4,T38,T177	Yes	T4,T37,T38	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T37,*T38	Yes	T4,T38,T177	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T37,T38	Yes	T4,T37,T38	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T228,T19,T229	Yes	T228,T19,T229	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T19,T229,T21	Yes	T19,T229,T21	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T19,T229,T21	Yes	T19,T229,T21	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T228,T19,T229	Yes	T228,T19,T229	OUTPUT
cio_usb_dp_i	Yes	Yes	T102,T39,T40	Yes	T39,T40,T28	INPUT
cio_usb_dn_i	Yes	Yes	T39,T40,T97	Yes	T39,T40,T28	INPUT
usb_rx_d_i	Yes	Yes	T39,T40,T97	Yes	T39,T40,T97	INPUT
cio_usb_dp_o	Yes	Yes	T37,T38,T39	Yes	T38,T39,T40	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T39,T40,T44	Yes	T39,T40,T44	OUTPUT
cio_usb_dn_o	Yes	Yes	T39,T40,T44	Yes	T39,T40,T97	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T39,T40,T44	Yes	T39,T40,T44	OUTPUT
usb_tx_se0_o	Yes	Yes	T39,T40,T44	Yes	T39,T40,T44	OUTPUT
usb_tx_d_o	Yes	Yes	T37,T38,T39	Yes	T38,T39,T40	OUTPUT
cio_sense_i	Yes	Yes	T39,T49,T50	Yes	T102,T39,T40	INPUT
usb_dp_pullup_o	Yes	Yes	T38,T39,T40	Yes	T37,T38,T39	OUTPUT
usb_dn_pullup_o	Yes	Yes	T39,T97,T98	Yes	T39,T97,T98	OUTPUT
usb_rx_enable_o	Yes	Yes	T39	Yes	T39,T40,T97	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T101	Yes	T101	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T37,T38,T87	Yes	T37,T38,T87	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T37,T38,T87	Yes	T37,T38,T87	OUTPUT
usb_aon_bus_reset_i	Yes	Yes	T98	Yes	T98	INPUT
usb_aon_sense_lost_i	Yes	Yes	T37,T85,T86	Yes	T37,T38,T87	INPUT
usb_aon_bus_not_idle_i	Yes	Yes	T37,T85,T86	Yes	T37,T85,T86	INPUT
usb_aon_wake_detect_active_i	Yes	Yes	T37,T85,T86	Yes	T37,T38,T87	INPUT
usb_ref_val_o	Yes	Yes	T39,T40,T44	Yes	T39,T40,T44	OUTPUT
usb_ref_pulse_o	Yes	Yes	T39,T40,T44	Yes	T39,T40,T44	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_pkt_sent_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_powered_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_disconnected_o	Yes	Yes	T111,T230,T101	Yes	T111,T230,T101	OUTPUT
intr_host_lost_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_link_reset_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_link_suspend_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_link_resume_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_av_out_empty_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_rx_full_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_av_overflow_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_link_in_err_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_link_out_err_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_frame_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT
intr_av_setup_empty_o	Yes	Yes	T111,T230,T231	Yes	T111,T230,T231	OUTPUT

*Tests covering at least one bit in the range