Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic 85.19 100.00 55.56 100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_por_aon_n_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T28,T32
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T33
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT31,T28,T32

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 25824 25298 0 0
selKnown1 133018 131599 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 25824 25298 0 0
T6 1 0 0 0
T9 2 1 0 0
T10 0 3 0 0
T12 38 37 0 0
T13 11 10 0 0
T31 1026 1025 0 0
T36 4 3 0 0
T49 7 24 0 0
T50 3 2 0 0
T51 4 3 0 0
T70 3 2 0 0
T71 2 1 0 0
T90 1 0 0 0
T91 1 0 0 0
T96 0 47 0 0
T130 1 0 0 0
T165 6 5 0 0
T212 0 2 0 0
T217 0 1 0 0
T246 3 2 0 0
T247 3 2 0 0
T248 2 1 0 0
T249 8 7 0 0
T250 4 3 0 0
T251 10 9 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 133018 131599 0 0
T1 2 1 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 5 4 0 0
T5 2 1 0 0
T24 1 0 0 0
T25 0 7 0 0
T31 576 575 0 0
T34 1 0 0 0
T49 8 13 0 0
T50 13 33 0 0
T51 10 24 0 0
T72 1 0 0 0
T92 2 1 0 0
T93 0 1 0 0
T103 1 0 0 0
T134 0 1 0 0
T162 0 1 0 0
T164 0 1 0 0
T165 18 36 0 0
T232 0 1 0 0
T246 26 44 0 0
T247 4 3 0 0
T248 23 22 0 0
T249 9 8 0 0
T250 11 10 0 0
T251 4 3 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT72,T73,T74
01CoveredT72,T73,T74
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT72,T73,T74
11CoveredT72,T73,T74

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 798 665 0 0
selKnown1 1771 747 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 798 665 0 0
T6 1 0 0 0
T9 2 1 0 0
T10 0 3 0 0
T12 38 37 0 0
T13 11 10 0 0
T36 4 3 0 0
T70 3 2 0 0
T71 2 1 0 0
T90 1 0 0 0
T91 1 0 0 0
T96 0 47 0 0
T130 1 0 0 0
T212 0 2 0 0
T217 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1771 747 0 0
T1 2 1 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 5 4 0 0
T5 2 1 0 0
T24 1 0 0 0
T25 0 7 0 0
T34 1 0 0 0
T72 1 0 0 0
T92 2 1 0 0
T93 0 1 0 0
T103 1 0 0 0
T134 0 1 0 0
T162 0 1 0 0
T164 0 1 0 0
T232 0 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T28,T32
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T33
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT31,T28,T32

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_out.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3823 3803 0 0
selKnown1 2960 2939 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3823 3803 0 0
T28 1 0 0 0
T31 1026 1025 0 0
T32 1026 1025 0 0
T33 161 160 0 0
T49 0 18 0 0
T61 19 18 0 0
T62 19 18 0 0
T63 1026 1025 0 0
T158 223 222 0 0
T159 183 182 0 0
T252 19 18 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2960 2939 0 0
T31 576 575 0 0
T32 576 575 0 0
T33 1 0 0 0
T49 0 6 0 0
T50 0 21 0 0
T51 0 15 0 0
T53 545 544 0 0
T54 545 544 0 0
T61 1 0 0 0
T62 1 0 0 0
T63 576 575 0 0
T158 1 0 0 0
T159 1 0 0 0
T165 0 19 0 0
T246 0 19 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT28,T49,T50
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T63
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT28,T49,T50

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].gen_mux_spi_host_d2.u_mux_dio_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 51 40 0 0
selKnown1 132 116 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 51 40 0 0
T49 7 6 0 0
T50 3 2 0 0
T51 4 3 0 0
T165 6 5 0 0
T246 3 2 0 0
T247 3 2 0 0
T248 2 1 0 0
T249 8 7 0 0
T250 4 3 0 0
T251 10 9 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 132 116 0 0
T49 8 7 0 0
T50 13 12 0 0
T51 10 9 0 0
T165 18 17 0 0
T246 26 25 0 0
T247 4 3 0 0
T248 23 22 0 0
T249 9 8 0 0
T250 11 10 0 0
T251 4 3 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T33
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T63
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT31,T32,T33

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_out.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3815 3795 0 0
selKnown1 135 119 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3815 3795 0 0
T30 1 0 0 0
T31 1025 1024 0 0
T32 1026 1025 0 0
T33 150 149 0 0
T49 0 11 0 0
T61 19 18 0 0
T62 19 18 0 0
T63 1026 1025 0 0
T158 221 220 0 0
T159 185 184 0 0
T252 19 18 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 135 119 0 0
T31 2 1 0 0
T32 2 1 0 0
T49 9 8 0 0
T50 22 21 0 0
T51 8 7 0 0
T52 1 0 0 0
T53 2 1 0 0
T54 2 1 0 0
T63 2 1 0 0
T165 0 16 0 0
T246 23 22 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT29,T30,T49
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T63
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT29,T30,T49

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].gen_mux_spi_host_d3.u_mux_dio_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 53 41 0 0
selKnown1 104 88 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 53 41 0 0
T49 11 10 0 0
T50 2 1 0 0
T51 7 6 0 0
T165 5 4 0 0
T246 3 2 0 0
T247 3 2 0 0
T248 6 5 0 0
T249 7 6 0 0
T250 3 2 0 0
T251 4 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 104 88 0 0
T49 4 3 0 0
T50 19 18 0 0
T51 8 7 0 0
T165 14 13 0 0
T246 23 22 0 0
T247 2 1 0 0
T248 10 9 0 0
T249 9 8 0 0
T250 4 3 0 0
T251 5 4 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T78
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T29
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT31,T32,T78

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_out.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4253 4231 0 0
selKnown1 477 462 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4253 4231 0 0
T31 1025 1024 0 0
T32 1025 1024 0 0
T33 285 284 0 0
T49 0 17 0 0
T50 0 11 0 0
T51 0 19 0 0
T61 1 0 0 0
T62 1 0 0 0
T63 1025 1024 0 0
T78 1 0 0 0
T80 1 0 0 0
T158 387 386 0 0
T159 368 367 0 0
T246 0 11 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 477 462 0 0
T29 1 0 0 0
T30 1 0 0 0
T31 117 116 0 0
T32 117 116 0 0
T49 9 8 0 0
T50 20 19 0 0
T51 9 8 0 0
T63 117 116 0 0
T165 8 7 0 0
T246 22 21 0 0
T247 0 4 0 0
T248 0 21 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T28,T32
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T29
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT31,T28,T32

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].gen_mux_spi_dev_d2.u_mux_dio_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 64 43 0 0
selKnown1 118 103 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 64 43 0 0
T30 1 0 0 0
T33 3 2 0 0
T49 11 10 0 0
T50 4 3 0 0
T51 5 4 0 0
T63 1 0 0 0
T81 1 0 0 0
T158 3 2 0 0
T159 3 2 0 0
T165 4 3 0 0
T247 0 1 0 0
T248 0 1 0 0
T249 0 7 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 118 103 0 0
T49 7 6 0 0
T50 12 11 0 0
T51 8 7 0 0
T165 13 12 0 0
T246 20 19 0 0
T247 8 7 0 0
T248 17 16 0 0
T249 8 7 0 0
T250 13 12 0 0
T251 7 6 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T78
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT53,T54,T49
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT31,T32,T78

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_out.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4235 4211 0 0
selKnown1 393 381 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4235 4211 0 0
T29 1 0 0 0
T30 1 0 0 0
T31 1025 1024 0 0
T32 1026 1025 0 0
T33 274 273 0 0
T49 0 14 0 0
T50 0 9 0 0
T51 0 14 0 0
T61 1 0 0 0
T62 1 0 0 0
T63 1026 1025 0 0
T78 1 0 0 0
T80 1 0 0 0
T158 0 384 0 0
T159 0 369 0 0
T246 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 393 381 0 0
T49 9 8 0 0
T50 15 14 0 0
T51 16 15 0 0
T53 154 153 0 0
T54 127 126 0 0
T165 9 8 0 0
T246 20 19 0 0
T247 11 10 0 0
T248 15 14 0 0
T249 5 4 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT31,T32,T78
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T29
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT31,T32,T78

Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].gen_mux_spi_dev_d3.u_mux_dio_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 71 50 0 0
selKnown1 105 89 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 71 50 0 0
T29 1 0 0 0
T30 1 0 0 0
T33 3 2 0 0
T49 9 8 0 0
T50 4 3 0 0
T51 11 10 0 0
T63 1 0 0 0
T81 1 0 0 0
T158 3 2 0 0
T159 3 2 0 0
T246 0 6 0 0
T247 0 2 0 0
T248 0 3 0 0
T249 0 4 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 105 89 0 0
T49 8 7 0 0
T50 12 11 0 0
T51 11 10 0 0
T165 10 9 0 0
T246 16 15 0 0
T247 11 10 0 0
T248 14 13 0 0
T249 5 4 0 0
T250 9 8 0 0
T251 3 2 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT31,T28,T32
01CoveredT31,T28,T32
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T82,T28
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT31,T28,T32
11CoveredT31,T28,T32

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3008 2984 0 0
selKnown1 3673 3641 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3008 2984 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 576 575 0 0
T32 576 575 0 0
T49 0 40 0 0
T50 0 23 0 0
T51 0 7 0 0
T52 1 0 0 0
T53 0 545 0 0
T54 0 545 0 0
T63 576 575 0 0
T99 1 0 0 0
T100 1 0 0 0
T101 1 0 0 0
T165 0 17 0 0
T189 1 0 0 0
T246 0 11 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3673 3641 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 1025 1024 0 0
T32 1025 1024 0 0
T33 126 125 0 0
T49 0 23 0 0
T50 0 7 0 0
T51 0 14 0 0
T61 1 0 0 0
T63 1025 1024 0 0
T82 1 0 0 0
T99 1 0 0 0
T100 1 0 0 0
T158 0 187 0 0
T159 0 147 0 0
T246 0 12 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT31,T28,T32
01CoveredT31,T28,T32
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T82,T28
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT31,T28,T32
11CoveredT31,T28,T32

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].gen_mux_iob0.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3007 2983 0 0
selKnown1 3669 3637 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3007 2983 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 576 575 0 0
T32 576 575 0 0
T49 0 40 0 0
T50 0 22 0 0
T51 0 7 0 0
T52 1 0 0 0
T53 0 545 0 0
T54 0 545 0 0
T63 576 575 0 0
T99 1 0 0 0
T100 1 0 0 0
T101 1 0 0 0
T165 0 17 0 0
T189 1 0 0 0
T246 0 12 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3669 3637 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 1025 1024 0 0
T32 1025 1024 0 0
T33 126 125 0 0
T49 0 22 0 0
T50 0 8 0 0
T51 0 14 0 0
T61 1 0 0 0
T63 1025 1024 0 0
T82 1 0 0 0
T99 1 0 0 0
T100 1 0 0 0
T158 0 187 0 0
T159 0 147 0 0
T246 0 11 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT31,T28,T32
01CoveredT31,T28,T32
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T28,T32
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT31,T28,T32
11CoveredT31,T28,T32

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 200 170 0 0
selKnown1 3645 3615 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 200 170 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 2 1 0 0
T32 2 1 0 0
T33 1 0 0 0
T49 0 17 0 0
T50 0 32 0 0
T51 0 12 0 0
T53 0 1 0 0
T54 0 1 0 0
T61 1 0 0 0
T62 1 0 0 0
T63 2 1 0 0
T99 1 0 0 0
T100 1 0 0 0
T165 0 26 0 0
T246 0 18 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3645 3615 0 0
T28 1 0 0 0
T31 1025 1024 0 0
T32 1026 1025 0 0
T33 115 114 0 0
T49 0 11 0 0
T50 0 5 0 0
T51 0 16 0 0
T61 1 0 0 0
T62 1 0 0 0
T63 1026 1025 0 0
T99 1 0 0 0
T100 1 0 0 0
T101 1 0 0 0
T158 0 185 0 0
T159 0 149 0 0
T246 0 8 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT31,T28,T32
01CoveredT31,T28,T32
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T28,T32
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT31,T28,T32
11CoveredT31,T28,T32

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].gen_mux_iob1.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 203 173 0 0
selKnown1 3647 3617 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 203 173 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 2 1 0 0
T32 2 1 0 0
T33 1 0 0 0
T49 0 18 0 0
T50 0 32 0 0
T51 0 12 0 0
T53 0 1 0 0
T54 0 1 0 0
T61 1 0 0 0
T62 1 0 0 0
T63 2 1 0 0
T99 1 0 0 0
T100 1 0 0 0
T165 0 26 0 0
T246 0 18 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 3647 3617 0 0
T28 1 0 0 0
T31 1025 1024 0 0
T32 1026 1025 0 0
T33 115 114 0 0
T49 0 12 0 0
T50 0 6 0 0
T51 0 16 0 0
T61 1 0 0 0
T62 1 0 0 0
T63 1026 1025 0 0
T99 1 0 0 0
T100 1 0 0 0
T101 1 0 0 0
T158 0 185 0 0
T159 0 149 0 0
T246 0 8 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT31,T28,T32
01CoveredT31,T28,T32
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T78
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT31,T28,T32
11CoveredT31,T28,T32

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 526 504 0 0
selKnown1 28052 28017 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 526 504 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 117 116 0 0
T32 117 116 0 0
T49 0 22 0 0
T50 0 18 0 0
T51 0 14 0 0
T63 117 116 0 0
T99 1 0 0 0
T100 1 0 0 0
T101 1 0 0 0
T165 0 12 0 0
T189 1 0 0 0
T190 1 0 0 0
T246 0 18 0 0
T247 0 6 0 0
T248 0 23 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 28052 28017 0 0
T26 3989 3988 0 0
T29 2 1 0 0
T31 1025 1024 0 0
T32 1025 1024 0 0
T33 319 318 0 0
T58 20 19 0 0
T78 2 1 0 0
T80 2 1 0 0
T116 2004 2003 0 0
T156 2012 2011 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT31,T28,T32
01CoveredT31,T28,T32
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T32,T78
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT31,T28,T32
11CoveredT31,T28,T32

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].gen_mux_iob2.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 521 499 0 0
selKnown1 28056 28021 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 521 499 0 0
T28 1 0 0 0
T29 1 0 0 0
T31 117 116 0 0
T32 117 116 0 0
T49 0 21 0 0
T50 0 18 0 0
T51 0 13 0 0
T63 117 116 0 0
T99 1 0 0 0
T100 1 0 0 0
T101 1 0 0 0
T165 0 12 0 0
T189 1 0 0 0
T190 1 0 0 0
T246 0 18 0 0
T247 0 6 0 0
T248 0 21 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 28056 28021 0 0
T26 3989 3988 0 0
T29 2 1 0 0
T31 1025 1024 0 0
T32 1025 1024 0 0
T33 319 318 0 0
T58 20 19 0 0
T78 2 1 0 0
T80 2 1 0 0
T116 2004 2003 0 0
T156 2012 2011 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT31,T41,T28
01CoveredT31,T41,T28
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T28,T32
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT31,T41,T28
11CoveredT31,T41,T28

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 599 554 0 0
selKnown1 28042 28005 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 599 554 0 0
T28 1 0 0 0
T31 2 1 0 0
T32 2 1 0 0
T33 1 0 0 0
T41 8 7 0 0
T42 2 1 0 0
T43 1 0 0 0
T63 0 1 0 0
T99 1 0 0 0
T100 1 0 0 0
T253 2 1 0 0
T254 0 30 0 0
T255 0 7 0 0
T256 0 7 0 0
T257 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 28042 28005 0 0
T26 3989 3988 0 0
T28 2 1 0 0
T31 1024 1023 0 0
T32 1025 1024 0 0
T33 308 307 0 0
T58 20 19 0 0
T78 2 1 0 0
T80 2 1 0 0
T116 2004 2003 0 0
T156 2012 2011 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT31,T41,T28
01CoveredT31,T41,T28
10Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT31,T28,T32
10Unreachable
11Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT31,T41,T28
11CoveredT31,T41,T28

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].gen_mux_iob3.u_mux_mio_in_raw.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 597 552 0 0
selKnown1 28039 28002 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 597 552 0 0
T28 1 0 0 0
T31 2 1 0 0
T32 2 1 0 0
T33 1 0 0 0
T41 8 7 0 0
T42 2 1 0 0
T43 1 0 0 0
T63 0 1 0 0
T99 1 0 0 0
T100 1 0 0 0
T253 2 1 0 0
T254 0 30 0 0
T255 0 7 0 0
T256 0 7 0 0
T257 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 28039 28002 0 0
T26 3989 3988 0 0
T28 2 1 0 0
T31 1024 1023 0 0
T32 1025 1024 0 0
T33 308 307 0 0
T58 20 19 0 0
T78 2 1 0 0
T80 2 1 0 0
T116 2004 2003 0 0
T156 2012 2011 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%