Module Definition
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Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T37
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T37
ODD - 1 Covered T1,T2,T24
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T37
ODD - 1 Covered T1,T2,T24
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
SyncReqAckAckNeedsReq 784587217 4537 0 0
SyncReqAckHoldReq 1050756267 4532 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 784587217 4537 0 0
T1 258206 4 0 0
T2 196468 2 0 0
T3 124139 1 0 0
T4 562763 5 0 0
T5 644540 2 0 0
T12 64530 0 0 0
T24 199875 2 0 0
T26 181646 0 0 0
T34 639650 1 0 0
T35 51017 0 0 0
T37 48127 3 0 0
T45 0 11 0 0
T46 0 14 0 0
T72 216429 1 0 0
T78 0 6 0 0
T80 0 6 0 0
T82 0 1 0 0
T85 0 6 0 0
T86 0 3 0 0
T90 12467 0 0 0
T92 277832 4 0 0
T103 367564 1 0 0
T117 0 3 0 0
T118 0 6 0 0
T119 24458 0 0 0
T120 51411 0 0 0
T121 73449 0 0 0
T122 37102 0 0 0
T123 42881 0 0 0
T219 26653 8 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1050756267 4532 0 0
T1 258206 4 0 0
T2 196468 2 0 0
T3 124139 1 0 0
T4 562763 5 0 0
T5 644540 2 0 0
T12 745 0 0 0
T24 199875 2 0 0
T26 15668 0 0 0
T34 639650 1 0 0
T35 672 0 0 0
T37 1358 3 0 0
T45 0 11 0 0
T46 0 13 0 0
T72 216429 1 0 0
T78 0 5 0 0
T80 0 5 0 0
T82 0 1 0 0
T85 0 6 0 0
T86 0 3 0 0
T90 249 0 0 0
T92 277832 4 0 0
T103 367564 1 0 0
T117 0 3 0 0
T118 0 6 0 0
T119 403 0 0 0
T120 834 0 0 0
T121 827 0 0 0
T122 553 0 0 0
T123 565 0 0 0
T219 109470 8 0 0