Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.36			88.36

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	88.36			88.36

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.36			88.36

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.36			88.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	92.47		87.18			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	366	65.12
Total Bits	7060	6238	88.36
Total Bits 0->1	3530	3122	88.44
Total Bits 1->0	3530	3116	88.27

Ports	562	366	65.12
Port Bits	7060	6238	88.36
Port Bits 0->1	3530	3122	88.44
Port Bits 1->0	3530	3116	88.27

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_main_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	INPUT
tl_main_i.a_opcode[1]	No	No		No		INPUT
tl_main_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T92,T172,T173	Yes	T92,T172,T173	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	No	No		No		OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T7,*T10,*T174	Yes	T7,T10,T14	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T4,T67,T68	Yes	T4,T67,T68	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T4,T67,T68	Yes	T4,T67,T68	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_uart0_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart0_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T4,T67,T68	Yes	T4,T67,T68	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T4,T67,T68	Yes	T4,T67,T68	INPUT
tl_uart0_i.d_error	No	No		No		INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T4,T67,T68	Yes	T4,T67,T68	INPUT
tl_uart0_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T67,T68	Yes	T4,T67,T68	INPUT
tl_uart0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart0_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,*T175,*T176	Yes	T4,T67,T68	INPUT
tl_uart0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T4,T67,T68	Yes	T4,T67,T68	INPUT
tl_uart0_i.d_sink	No	No		No		INPUT
tl_uart0_i.d_source[1:0]	Yes	Yes	*T101,*T193,*T312	Yes	T101,T193,T312	INPUT
tl_uart0_i.d_source[5:2]	No	No		No		INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[0]	No	No		No		INPUT
tl_uart0_i.d_size[1]	Yes	Yes	T4,T175,T176	Yes	T4,T67,T68	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T4,*T67,*T68	Yes	T4,T67,T68	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T4,T67,T68	Yes	T4,T67,T68	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T26,T31,T313	Yes	T26,T31,T313	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart1_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T26,T31,T313	Yes	T26,T31,T313	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_uart1_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart1_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T26,T31,T175	Yes	T26,T31,T175	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T26,T31,T175	Yes	T26,T31,T175	INPUT
tl_uart1_i.d_error	No	No		No		INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T26,T31,T313	Yes	T26,T31,T313	INPUT
tl_uart1_i.d_user.rsp_intg[1:0]	Yes	Yes	T26,T31,T175	Yes	T26,T31,T175	INPUT
tl_uart1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart1_i.d_user.rsp_intg[5:4]	Yes	Yes	*T175,*T314,*T101	Yes	T26,T31,T175	INPUT
tl_uart1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T26,T31,T175	Yes	T26,T31,T175	INPUT
tl_uart1_i.d_sink	No	No		No		INPUT
tl_uart1_i.d_source[1:0]	Yes	Yes	*T101,*T26,*T31	Yes	T101,T26,T31	INPUT
tl_uart1_i.d_source[5:2]	No	No		No		INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[0]	No	No		No		INPUT
tl_uart1_i.d_size[1]	Yes	Yes	T175,T314,T101	Yes	T26,T31,T175	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T26,*T31,*T313	Yes	T26,T31,T313	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T26,T31,T175	Yes	T26,T31,T175	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T31,T153,T315	Yes	T31,T153,T315	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart2_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T31,T153,T315	Yes	T31,T153,T315	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_uart2_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart2_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T31,T153,T175	Yes	T31,T153,T175	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T31,T153,T175	Yes	T31,T153,T175	INPUT
tl_uart2_i.d_error	No	No		No		INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T31,T153,T315	Yes	T31,T153,T315	INPUT
tl_uart2_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T153,T175	Yes	T31,T153,T175	INPUT
tl_uart2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart2_i.d_user.rsp_intg[5:4]	Yes	Yes	*T175,*T314,*T101	Yes	T31,T153,T175	INPUT
tl_uart2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T31,T153,T175	Yes	T31,T153,T175	INPUT
tl_uart2_i.d_sink	No	No		No		INPUT
tl_uart2_i.d_source[1:0]	Yes	Yes	*T101,*T31,*T153	Yes	T101,T31,T153	INPUT
tl_uart2_i.d_source[5:2]	No	No		No		INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[0]	No	No		No		INPUT
tl_uart2_i.d_size[1]	Yes	Yes	T175,T314,T101	Yes	T31,T153,T175	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T31,*T153,*T315	Yes	T31,T153,T315	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T31,T153,T175	Yes	T31,T153,T175	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T34,T35,T31	Yes	T34,T35,T31	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart3_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T34,T35,T31	Yes	T34,T35,T31	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_uart3_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart3_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T34,T35,T31	Yes	T34,T35,T31	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T34,T35,T31	Yes	T34,T35,T31	INPUT
tl_uart3_i.d_error	No	No		No		INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T34,T35,T31	Yes	T34,T35,T31	INPUT
tl_uart3_i.d_user.rsp_intg[1:0]	Yes	Yes	T34,T35,T31	Yes	T34,T35,T31	INPUT
tl_uart3_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart3_i.d_user.rsp_intg[5:4]	Yes	Yes	*T175,*T314,*T101	Yes	T34,T35,T31	INPUT
tl_uart3_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T34,T35,T31	Yes	T34,T35,T31	INPUT
tl_uart3_i.d_sink	No	No		No		INPUT
tl_uart3_i.d_source[1:0]	Yes	Yes	*T101,*T34,*T35	Yes	T101,T34,T35	INPUT
tl_uart3_i.d_source[5:2]	No	No		No		INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[0]	No	No		No		INPUT
tl_uart3_i.d_size[1]	Yes	Yes	T175,T314,T101	Yes	T34,T35,T31	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T34,*T35,*T31	Yes	T34,T35,T31	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T34,T35,T31	Yes	T34,T35,T31	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T31,T233,T32	Yes	T31,T233,T32	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T31,T233,T32	Yes	T31,T233,T32	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_i2c0_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c0_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	INPUT
tl_i2c0_i.d_error	No	No		No		INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T31,T233,T32	Yes	T31,T233,T32	INPUT
tl_i2c0_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	INPUT
tl_i2c0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T175,T238,T100	Yes	T31,T175,T233	INPUT
tl_i2c0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	INPUT
tl_i2c0_i.d_sink	No	No		No		INPUT
tl_i2c0_i.d_source[1:0]	Yes	Yes	*T100,*T31,*T175	Yes	T100,T31,T175	INPUT
tl_i2c0_i.d_source[5:2]	No	No		No		INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[0]	No	No		No		INPUT
tl_i2c0_i.d_size[1]	Yes	Yes	T175,T238,T100	Yes	T31,T175,T233	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T31,*T233,*T32	Yes	T31,T233,T32	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T236,T31,T237	Yes	T236,T31,T237	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c1_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T236,T31,T237	Yes	T236,T31,T237	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_i2c1_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c1_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T236,T31,T175	Yes	T236,T31,T175	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T236,T31,T175	Yes	T236,T31,T175	INPUT
tl_i2c1_i.d_error	No	No		No		INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T236,T31,T237	Yes	T236,T31,T237	INPUT
tl_i2c1_i.d_user.rsp_intg[1:0]	Yes	Yes	T236,T31,T175	Yes	T236,T31,T175	INPUT
tl_i2c1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c1_i.d_user.rsp_intg[5:4]	Yes	Yes	*T175,T238,T100	Yes	T236,T31,T175	INPUT
tl_i2c1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T236,T31,T175	Yes	T236,T31,T175	INPUT
tl_i2c1_i.d_sink	No	No		No		INPUT
tl_i2c1_i.d_source[1:0]	Yes	Yes	*T100,*T236,*T31	Yes	T100,T236,T31	INPUT
tl_i2c1_i.d_source[5:2]	No	No		No		INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[0]	No	No		No		INPUT
tl_i2c1_i.d_size[1]	Yes	Yes	T175,T238,T100	Yes	T236,T31,T175	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T236,*T31,*T237	Yes	T236,T31,T237	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T236,T31,T175	Yes	T236,T31,T175	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T31,T233,T32	Yes	T31,T233,T32	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c2_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T31,T233,T32	Yes	T31,T233,T32	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_i2c2_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c2_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	INPUT
tl_i2c2_i.d_error	No	No		No		INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T31,T233,T32	Yes	T31,T233,T32	INPUT
tl_i2c2_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	INPUT
tl_i2c2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c2_i.d_user.rsp_intg[5:4]	Yes	Yes	*T175,T238,T100	Yes	T31,T175,T233	INPUT
tl_i2c2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	INPUT
tl_i2c2_i.d_sink	No	No		No		INPUT
tl_i2c2_i.d_source[1:0]	Yes	Yes	*T100,*T31,*T175	Yes	T100,T31,T175	INPUT
tl_i2c2_i.d_source[5:2]	No	No		No		INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[0]	No	No		No		INPUT
tl_i2c2_i.d_size[1]	Yes	Yes	T175,T238,T100	Yes	T31,T175,T233	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T31,*T233,*T32	Yes	T31,T233,T32	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T31,T175,T233	Yes	T31,T175,T233	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T155,T119,T316	Yes	T155,T119,T316	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pattgen_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T155,T119,T316	Yes	T155,T119,T316	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_pattgen_o.a_opcode[1]	No	No		No		OUTPUT
tl_pattgen_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T155,T119,T316	Yes	T155,T119,T316	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T155,T119,T316	Yes	T155,T119,T316	INPUT
tl_pattgen_i.d_error	No	No		No		INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T155,T119,T316	Yes	T155,T119,T316	INPUT
tl_pattgen_i.d_user.rsp_intg[1:0]	Yes	Yes	T155,T119,T316	Yes	T155,T119,T316	INPUT
tl_pattgen_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pattgen_i.d_user.rsp_intg[4]	No	No		Yes	T155,T119,T316	INPUT
tl_pattgen_i.d_user.rsp_intg[5]	Yes	Yes	*T155,*T119,*T316	Yes	T155,T119,T316	INPUT
tl_pattgen_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T155,T119,T316	Yes	T155,T119,T316	INPUT
tl_pattgen_i.d_sink	No	No		No		INPUT
tl_pattgen_i.d_source[0]	No	No		No		INPUT
tl_pattgen_i.d_source[1]	Yes	Yes	*T155,*T119,*T316	Yes	T155,T119,T316	INPUT
tl_pattgen_i.d_source[5:2]	No	No		No		INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[0]	No	No		No		INPUT
tl_pattgen_i.d_size[1]	No	No		Yes	T155,T119,T316	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T155,*T119,*T316	Yes	T155,T119,T316	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T155,T119,T316	Yes	T155,T119,T316	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T127,T31,T154	Yes	T127,T31,T154	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T127,T31,T154	Yes	T127,T31,T154	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_pwm_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T127,T31,T154	Yes	T127,T31,T154	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T127,T31,T154	Yes	T127,T31,T154	INPUT
tl_pwm_aon_i.d_error	No	No		No		INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T127,T31,T154	Yes	T127,T31,T154	INPUT
tl_pwm_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T127,T31,T154	Yes	T127,T31,T154	INPUT
tl_pwm_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwm_aon_i.d_user.rsp_intg[4]	No	No		Yes	T127,T31,T154	INPUT
tl_pwm_aon_i.d_user.rsp_intg[5]	Yes	Yes	*T127,*T31,*T154	Yes	T127,T31,T154	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T127,T31,T154	Yes	T127,T31,T154	INPUT
tl_pwm_aon_i.d_sink	No	No		No		INPUT
tl_pwm_aon_i.d_source[0]	No	No		No		INPUT
tl_pwm_aon_i.d_source[1]	Yes	Yes	*T127,*T31,*T154	Yes	T127,T31,T154	INPUT
tl_pwm_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[0]	No	No		No		INPUT
tl_pwm_aon_i.d_size[1]	No	No		Yes	T127,T31,T154	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T127,*T31,*T154	Yes	T127,T31,T154	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T127,T31,T154	Yes	T127,T31,T154	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_gpio_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_gpio_o.a_opcode[1]	No	No		No		OUTPUT
tl_gpio_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	No	No		No		INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T36,T233,T78	Yes	T36,T233,T78	INPUT
tl_gpio_i.d_user.rsp_intg[1:0]	Yes	Yes	T36,T233,T78	Yes	T36,T31,T45	INPUT
tl_gpio_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_gpio_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T36,T233,T78	Yes	T36,T31,T45	INPUT
tl_gpio_i.d_sink	No	No		No		INPUT
tl_gpio_i.d_source[1:0]	Yes	Yes	*T100,*T1,*T4	Yes	T100,T1,T2	INPUT
tl_gpio_i.d_source[5:2]	No	No		No		INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[0]	No	No		No		INPUT
tl_gpio_i.d_size[1]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T155,T26,T31	Yes	T155,T26,T31	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_device_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T155,T26,T31	Yes	T155,T26,T31	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_spi_device_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_device_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T155,T26,T31	Yes	T155,T26,T31	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T155,T26,T31	Yes	T155,T26,T31	INPUT
tl_spi_device_i.d_error	No	No		No		INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T155,T26,T58	Yes	T155,T26,T58	INPUT
tl_spi_device_i.d_user.rsp_intg[1:0]	Yes	Yes	T155,T26,T31	Yes	T155,T26,T31	INPUT
tl_spi_device_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_device_i.d_user.rsp_intg[5:4]	Yes	Yes	T26,T58,T156	Yes	T155,T26,T31	INPUT
tl_spi_device_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T155,T26,T31	Yes	T155,T26,T58	INPUT
tl_spi_device_i.d_sink	No	No		No		INPUT
tl_spi_device_i.d_source[1:0]	Yes	Yes	*T17,*T155,*T26	Yes	T17,T155,T26	INPUT
tl_spi_device_i.d_source[5:2]	No	No		No		INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[0]	No	No		No		INPUT
tl_spi_device_i.d_size[1]	Yes	Yes	T26,T58,T156	Yes	T155,T26,T31	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T155,*T26,*T31	Yes	T155,T26,T31	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T155,T26,T31	Yes	T155,T26,T31	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T155,T154,T272	Yes	T155,T154,T272	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_timer_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T155,T154,T272	Yes	T155,T154,T272	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_rv_timer_o.a_opcode[1]	No	No		No		OUTPUT
tl_rv_timer_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T155,T154,T272	Yes	T155,T154,T272	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T155,T154,T272	Yes	T155,T154,T272	INPUT
tl_rv_timer_i.d_error	No	No		No		INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T155,T272,T273	Yes	T155,T272,T273	INPUT
tl_rv_timer_i.d_user.rsp_intg[1:0]	Yes	Yes	T155,T154,T272	Yes	T155,T154,T272	INPUT
tl_rv_timer_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_timer_i.d_user.rsp_intg[5:4]	Yes	Yes	T317,*T17,*T155	Yes	T155,T154,T272	INPUT
tl_rv_timer_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T154,T272,T273	Yes	T155,T154,T272	INPUT
tl_rv_timer_i.d_sink	No	No		No		INPUT
tl_rv_timer_i.d_source[1:0]	Yes	Yes	*T17,*T155,*T154	Yes	T17,T155,T154	INPUT
tl_rv_timer_i.d_source[5:2]	No	No		No		INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[0]	No	No		No		INPUT
tl_rv_timer_i.d_size[1]	Yes	Yes	T317,T17	Yes	T155,T154,T272	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T155,*T154,*T272	Yes	T155,T154,T272	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T155,T154,T272	Yes	T155,T154,T272	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T285,T25	Yes	T4,T285,T25	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T285,T25	Yes	T4,T285,T25	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_pwrmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T285,T25	Yes	T4,T285,T25	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T285,T25	Yes	T4,T285,T25	INPUT
tl_pwrmgr_aon_i.d_error	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T285,T25	Yes	T4,T285,T25	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T285,T25	Yes	T4,T285,T25	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T25,*T27,*T64	Yes	T4,T285,T25	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T285,T25	Yes	T4,T285,T25	INPUT
tl_pwrmgr_aon_i.d_sink	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[0]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[1]	Yes	Yes	*T4,*T285,*T25	Yes	T4,T285,T25	INPUT
tl_pwrmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_size[1]	Yes	Yes	T25,T27,T64	Yes	T4,T285,T25	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T285,*T25	Yes	T4,T285,T25	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T285,T25	Yes	T4,T285,T25	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_rstmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[0]	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[1]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_rstmgr_aon_i.d_size[1]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T34,T4,T72	Yes	T34,T4,T72	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T24,T34	Yes	T2,T24,T34	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_clkmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T34,T72,T73	Yes	T34,T72,T73	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T34,T4	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,T4,*T5	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T34,T4	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[0]	No	No		Yes	T10,T174,T202	INPUT
tl_clkmgr_aon_i.d_source[1]	Yes	Yes	*T1,*T34,*T4	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_clkmgr_aon_i.d_size[1]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T34,*T4,*T72	Yes	T34,T4,T72	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_pinmux_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	No	No		No		INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[2]	No	No		No		INPUT
tl_pinmux_aon_i.d_user.rsp_intg[5:3]	Yes	Yes	*T49,*T50,*T51	Yes	T49,T50,T51	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	No	No		No		INPUT
tl_pinmux_aon_i.d_source[0]	No	No		No		INPUT
tl_pinmux_aon_i.d_source[5:1]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_otp_ctrl__core_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[1:0]	Yes	Yes	*T10,*T174,*T202	Yes	T10,T174,T202	INPUT
tl_otp_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T5,*T155,*T134	Yes	T5,T155,T134	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_otp_ctrl__prim_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_valid	No	No		No		OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T5	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[1:0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T4,T5	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[4:3]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[5]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T5	INPUT
tl_otp_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T4,T5	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	No	No		No		INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T34,T67,T68	Yes	T34,T67,T68	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T34,T67,T68	Yes	T34,T67,T68	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_lc_ctrl_o.a_opcode[1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T34,T67,T68	Yes	T34,T67,T68	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T34,T67,T68	Yes	T34,T67,T68	INPUT
tl_lc_ctrl_i.d_error	No	No		No		INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T67,T68,T26	Yes	T67,T68,T26	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[1:0]	Yes	Yes	T70,T212,T210	Yes	T70,T212,T210	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_user.rsp_intg[5:4]	Yes	Yes	T26,T70,*T7	Yes	T34,T67,T68	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T67,T68,T26	Yes	T34,T67,T68	INPUT
tl_lc_ctrl_i.d_sink	No	No		No		INPUT
tl_lc_ctrl_i.d_source[1:0]	Yes	Yes	*T7,*T16,*T318	Yes	T7,T16,T318	INPUT
tl_lc_ctrl_i.d_source[5:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[0]	No	No		No		INPUT
tl_lc_ctrl_i.d_size[1]	Yes	Yes	T26,T70,T7	Yes	T34,T67,T68	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T26,*T70,*T7	Yes	T34,T67,T68	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T34,T67,T68	Yes	T34,T67,T68	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T155,T124,T37	Yes	T155,T124,T37	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T155,T124,T37	Yes	T155,T124,T37	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[2]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[5:3]	Yes	Yes	*T49,*T50,*T51	Yes	T49,T50,T51	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T17,*T1,*T4	Yes	T17,T1,T2	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_alert_handler_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_alert_handler_o.a_opcode[1]	No	No		No		OUTPUT
tl_alert_handler_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	INPUT
tl_alert_handler_i.d_error	No	No		No		INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	INPUT
tl_alert_handler_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	INPUT
tl_alert_handler_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_alert_handler_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	INPUT
tl_alert_handler_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	INPUT
tl_alert_handler_i.d_sink	No	No		No		INPUT
tl_alert_handler_i.d_source[0]	No	No		No		INPUT
tl_alert_handler_i.d_source[1]	Yes	Yes	*T1,*T92,*T93	Yes	T1,T92,T93	INPUT
tl_alert_handler_i.d_source[5:2]	No	No		No		INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[0]	No	No		No		INPUT
tl_alert_handler_i.d_size[1]	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T1,*T92,*T93	Yes	T1,T92,T93	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T1,T92,T93	Yes	T1,T92,T93	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T67,T68,T120	Yes	T67,T68,T120	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T67,T68,T120	Yes	T67,T68,T120	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T67,T68,T120	Yes	T67,T68,T120	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T67,T68,T120	Yes	T67,T68,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[5:0]	Yes	Yes	*T120,*T129,T218	Yes	T120,T129,T218	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T120,T129,T218	Yes	T67,T68,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T218,*T64,*T65	Yes	T67,T68,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T120,T129,T218	Yes	T67,T68,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[1:0]	Yes	Yes	*T17,*T120,*T129	Yes	T17,T67,T68	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1]	Yes	Yes	T218,T64,T65	Yes	T67,T68,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T120,*T129,*T218	Yes	T120,T129,T218	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T67,T68,T120	Yes	T67,T68,T120	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T5	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[1:0]	Yes	Yes	*T99,*T189,*T190	Yes	T99,T189,T190	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_aon_timer_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	INPUT
tl_aon_timer_aon_i.d_error	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	INPUT
tl_aon_timer_aon_i.d_sink	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[0]	No	No		Yes	T14,T193,T319	INPUT
tl_aon_timer_aon_i.d_source[1]	Yes	Yes	*T1,*T4,*T92	Yes	T1,T4,T92	INPUT
tl_aon_timer_aon_i.d_source[5:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[0]	No	No		No		INPUT
tl_aon_timer_aon_i.d_size[1]	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T92	Yes	T1,T4,T92	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T1,T4,T92	Yes	T1,T4,T92	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T25,T37,T274	Yes	T25,T37,T274	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T25,T37,T274	Yes	T25,T37,T274	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T25,T37,T274	Yes	T25,T37,T274	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T25,T37,T274	Yes	T25,T37,T274	INPUT
tl_sysrst_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T25,T37,T274	Yes	T25,T37,T274	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T25,T37,T274	Yes	T25,T37,T274	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T25,T274,T27	Yes	T25,T37,T274	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T25,T274,T27	Yes	T25,T37,T274	INPUT
tl_sysrst_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[1:0]	Yes	Yes	*T101,*T17,*T25	Yes	T101,T17,T25	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_size[1]	Yes	Yes	T25,T274,T27	Yes	T25,T37,T274	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T25,*T37,*T274	Yes	T25,T37,T274	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T25,T37,T274	Yes	T25,T37,T274	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T88,T37,T6	Yes	T88,T37,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T88,T37,T6	Yes	T88,T37,T6	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_adc_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T88,T37,T6	Yes	T88,T37,T6	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T88,T37,T6	Yes	T88,T37,T6	INPUT
tl_adc_ctrl_aon_i.d_error	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T88,T37,T233	Yes	T88,T37,T6	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T88,T37,T6	Yes	T88,T37,T6	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T6,T8,T198	Yes	T88,T37,T6	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T88,T37,T6	Yes	T88,T37,T6	INPUT
tl_adc_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[0]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[1]	Yes	Yes	*T88,*T37,*T31	Yes	T88,T37,T6	INPUT
tl_adc_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_size[1]	Yes	Yes	T6,T8,T198	Yes	T88,T37,T6	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T88,*T37,*T31	Yes	T88,T37,T6	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T88,T37,T6	Yes	T88,T37,T6	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_ast_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T7,*T10,*T14	Yes	T7,T10,T14	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T49,T50,T51	Yes	T49,T50,T51	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	OUTPUT
tl_ast_o.a_opcode[1]	No	No		No		OUTPUT
tl_ast_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	No	No		No		INPUT
tl_ast_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_ast_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T2,T3	INPUT
tl_ast_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	No	No		No		INPUT
tl_ast_i.d_source[0]	No	No		No		INPUT
tl_ast_i.d_source[5:1]	Yes	Yes	*T64,*T65,*T66	Yes	T67,T68,T69	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[0]	No	No		No		INPUT
tl_ast_i.d_size[1]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	No	No		No		INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range