584c3d46af| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.818m | 2.557ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.599m | 2.027ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.823m | 2.620ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.033m | 2.921ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | chip_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V1 | xbar_smoke | xbar_smoke | 0 | 100 | 0.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.002m | 3.799ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.002m | 3.799ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.002m | 3.799ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 12.194m | 4.161ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 12.194m | 4.161ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 12.934m | 4.921ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 13.126m | 4.115ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 11.297m | 3.781ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 43.128m | 12.957ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 34.760m | 7.863ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 19.287m | 8.777ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 65 | 220 | 29.55 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.380m | 4.823ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.380m | 4.823ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.576m | 3.607ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 9.248m | 5.877ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.907m | 4.142ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 18.946m | 12.042ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 14.122m | 9.436ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 15.136m | 8.561ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 15.927m | 8.774ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.534m | 3.403ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 26.520m | 8.864ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 16.006m | 5.676ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 16.006m | 5.676ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 19.236m | 8.282ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 1.073h | 25.989ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 14.838m | 3.911ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.389m | 5.251ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 56.311m | 18.596ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 6.294m | 3.303ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.290m | 8.010ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.351m | 2.946ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 31.339m | 8.281ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.808m | 2.742ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.645m | 5.542ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.078m | 2.591ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 6.305m | 2.908ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 17.733m | 6.951ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.902m | 5.012ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.747m | 2.927ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.902m | 5.012ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.462m | 3.462ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.960m | 3.313ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 6.009m | 2.824ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.160m | 2.792ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.885m | 3.096ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 11.077m | 3.682ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 6.063m | 2.445ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 7.369m | 2.928ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.126m | 3.319ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 26.143m | 6.219ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.854m | 6.570ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 10.637m | 5.996ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 6.061m | 2.875ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 6.539m | 3.017ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.451m | 2.664ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.986m | 3.327ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.802m | 2.583ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.147m | 3.327ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 14.575m | 5.609ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 4.016h | 79.016ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 58.803m | 14.518ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 4.888m | 3.818ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 11.152m | 4.733ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 7.415m | 11.256ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.277h | 57.785ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.310h | 64.711ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_illegal_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | xbar_base_random_sequence | xbar_random | 0 | 100 | 0.00 | ||
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 0 | 100 | 0.00 | ||
| xbar_smoke_large_delays | 0 | 100 | 0.00 | ||||
| xbar_smoke_slow_rsp | 0 | 100 | 0.00 | ||||
| xbar_random_zero_delays | 0 | 100 | 0.00 | ||||
| xbar_random_large_delays | 0 | 100 | 0.00 | ||||
| xbar_random_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_error_cases | xbar_error_random | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 0 | 100 | 0.00 | ||
| xbar_access_same_device_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 0 | 100 | 0.00 | ||
| V2 | xbar_stress_all | xbar_stress_all | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_error | 0 | 100 | 0.00 | ||||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_reset_error | 0 | 100 | 0.00 | ||||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 58.803m | 14.518ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 59.338m | 23.308ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.039h | 14.511ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 56.531m | 11.286ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.020h | 15.833ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.212h | 15.473ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.132h | 14.823ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.090h | 14.630ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 51.239m | 11.227ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.232h | 16.371ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.035h | 15.571ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 56.313m | 15.460ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 53.723m | 14.302ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.555h | 18.156ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.899h | 23.926ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.654h | 23.610ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.605h | 23.521ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.700h | 23.893ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.276h | 18.208ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.581h | 22.872ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.627h | 24.074ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.639h | 24.196ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.874h | 23.173ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 40.989m | 11.162ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.040h | 15.284ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 59.031m | 14.406ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.017h | 14.747ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 52.249m | 13.577ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 45.571m | 11.454ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.224h | 15.565ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.016h | 14.066ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 58.597m | 13.612ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 53.673m | 14.488ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 1.034h | 11.405ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 57.556m | 15.148ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.067h | 15.295ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.083h | 16.003ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.263h | 15.701ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.127h | 15.737ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.378h | 14.757ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.065h | 15.715ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.283h | 17.498ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 6.011m | 3.721ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 6.294m | 3.303ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.444m | 2.947ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 6.055m | 3.270ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 43.041m | 12.821ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.344m | 18.427ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.344m | 18.427ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.463m | 3.993ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 8.854m | 6.570ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.463m | 3.993ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 17.756m | 10.234ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 17.756m | 10.234ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 10.170m | 8.165ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.346m | 4.717ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 18.785m | 6.056ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 6.055m | 3.270ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.575m | 3.150ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.150m | 3.027ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 10.093m | 4.737ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 10.316m | 5.583ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 9.375m | 5.550ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 11.870m | 4.690ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 25.870m | 10.942ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.369m | 4.442ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.794m | 4.360ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.741m | 4.048ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.087m | 4.699ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.313m | 4.373ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.876m | 4.962ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 19.236m | 8.282ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 15.966m | 12.005ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.741m | 4.048ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.087m | 4.699ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 14.838m | 3.911ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.389m | 5.251ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 56.311m | 18.596ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 6.294m | 3.303ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.290m | 8.010ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.351m | 2.946ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 31.339m | 8.281ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.808m | 2.742ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.645m | 5.542ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.078m | 2.591ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.917m | 2.648ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 13.308m | 4.838ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 22.457m | 7.495ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.086h | 24.800ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.899m | 3.275ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.356m | 3.853ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 32.161m | 12.454ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.153m | 2.798ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 11.744m | 5.242ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 41.874m | 27.309ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 1.499h | 32.977ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 19.236m | 8.282ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 12.354m | 4.388ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.859m | 3.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.386m | 5.197ms | 98 | 100 | 98.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 27.363m | 7.747ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 32.841m | 7.326ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 11.223m | 4.379ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 14.388m | 6.527ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.411m | 3.152ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 19.811m | 7.736ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 27.393m | 24.136ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 8.111m | 3.207ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 5.757m | 3.262ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 12.464m | 4.732ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 27.393m | 24.136ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 27.393m | 24.136ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.214h | 19.978ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.214h | 19.978ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.354m | 5.721ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.344m | 18.427ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.897h | 35.017ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.352m | 2.142ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 26.915m | 7.180ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.352m | 2.142ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 32.841m | 7.326ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.955m | 3.021ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 40.940m | 19.362ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 22.088m | 6.053ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.389m | 5.251ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 11.434m | 4.470ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 14.838m | 3.911ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.382h | 45.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 40.940m | 19.362ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.909m | 4.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 35.077m | 9.598ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 12.554m | 6.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.382h | 45.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 12.554m | 6.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 12.554m | 6.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 12.554m | 6.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 12.554m | 6.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.386m | 5.197ms | 98 | 100 | 98.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 22.620m | 6.448ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 11.522m | 5.162ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 11.522m | 5.162ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.480m | 3.236ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.351m | 2.946ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.575m | 3.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 7.262m | 3.242ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 39.841m | 9.325ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 16.284m | 5.476ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 17.186m | 5.347ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 18.588m | 5.689ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 11.685m | 4.700ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 35.077m | 9.598ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 31.339m | 8.281ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 28.177m | 7.699ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 43.041m | 12.821ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.088h | 16.253ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 5.612m | 3.325ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.037m | 3.124ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.808m | 2.742ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 35.077m | 9.598ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 16.667m | 12.330ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.500m | 2.147ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.697m | 3.256ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.150m | 3.027ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 11.204m | 5.822ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 18.946m | 12.042ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 15.136m | 8.561ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 15.927m | 8.774ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 6.169m | 3.456ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 16.667m | 12.330ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 16.667m | 12.330ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 16.667m | 12.330ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 25.422m | 8.163ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 12.554m | 6.303ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.382h | 45.107ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.550m | 4.763ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 23.931m | 7.904ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 27.103m | 8.828ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.563m | 9.483ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 16.667m | 12.330ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 35.077m | 9.598ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.710m | 8.397ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 19.987m | 8.880ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_lc | 15.966m | 12.005ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.369m | 4.442ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.794m | 4.360ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.741m | 4.048ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 11.087m | 4.699ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.313m | 4.373ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.876m | 4.962ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 18.946m | 12.042ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 15.136m | 8.561ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 15.927m | 8.774ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 5.018m | 3.440ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.599m | 3.040ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.730m | 3.837ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.604m | 3.376ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 38.126m | 27.980ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.560h | 48.982ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.652h | 49.661ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 20.139m | 8.924ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.581h | 46.551ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 38.126m | 27.980ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.462m | 2.038ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.080m | 2.611ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 1.926m | 2.343ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 16.667m | 12.330ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 40.940m | 19.362ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 12.109m | 4.180ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 35.077m | 9.598ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 10.789m | 5.430ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.147m | 2.768ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 40.940m | 19.362ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 12.109m | 4.180ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 35.077m | 9.598ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 10.789m | 5.430ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.147m | 2.768ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 16.667m | 12.330ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 11.223m | 4.212ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 6.169m | 3.456ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.550m | 4.763ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 23.931m | 7.904ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 27.103m | 8.828ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.563m | 9.483ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 16.667m | 12.330ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.520h | 27.941ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 11.126m | 7.652ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 27.141m | 24.522ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 8.138m | 7.270ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 16.021m | 7.305ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 15.211m | 6.220ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 31.119m | 26.631ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 30.473m | 15.591ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 17.756m | 10.234ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 28.945m | 12.714ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.475m | 4.984ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 11.126m | 7.652ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 9.434m | 5.522ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 53.830m | 43.881ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 10.323m | 7.114ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 9.825m | 4.494ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 48.970m | 19.620ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 19.811m | 7.736ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 28.359m | 12.392ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 1.039h | 26.769ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.531m | 2.785ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.386m | 5.197ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.710m | 8.397ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.710m | 8.397ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 28.359m | 12.392ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 48.970m | 19.620ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 10.475m | 4.984ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.854m | 6.570ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 7.670m | 4.340ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 16.275m | 7.860ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 8.489m | 4.670ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 28.191m | 11.470ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.930m | 2.796ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.386m | 5.197ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 34.430m | 8.180ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 21.843m | 6.162ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.641m | 3.947ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.396m | 5.405ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.928m | 2.202ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.907m | 3.274ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 58.803m | 14.518ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 14.196m | 8.420ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 12.347m | 5.286ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.345m | 3.033ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.780m | 3.021ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 10.789m | 5.430ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.645m | 5.542ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 16.537m | 9.632ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 11.677m | 8.391ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 19.987m | 8.880ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.386m | 5.197ms | 98 | 100 | 98.00 |
| chip_sw_data_integrity_escalation | 16.006m | 5.676ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 3.336m | 2.432ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.483m | 3.293ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 8.927m | 3.997ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 10.021m | 4.437ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 34.115m | 7.681ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 1.731h | 31.644ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 50.496m | 11.850ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.865m | 3.130ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 11.204m | 5.822ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.386m | 5.197ms | 98 | 100 | 98.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.668m | 3.342ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 28.191m | 11.470ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 9.955m | 5.630ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.237m | 3.814ms | 89 | 90 | 98.89 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 28.013m | 13.323ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 27.363m | 7.747ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 34.430m | 8.180ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 23.585m | 7.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.591h | 255.065ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 21.975m | 11.910ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 27.817m | 14.307ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 7.670m | 4.340ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.478m | 3.843ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 10.419m | 6.440ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 15.136m | 8.561ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 885 | 2644 | 33.47 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.985m | 3.126ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 4.293h | 71.543ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 25.040m | 6.394ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 33.240m | 10.651ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 33.607m | 10.839ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 33.345m | 11.704ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 33.675m | 24.948ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 42.012m | 32.251ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 53.950m | 26.902ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 1.524h | 26.327ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.162m | 3.551ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 10.434m | 3.490ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 38.737m | 7.007ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 39.928m | 9.983ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 13.248m | 3.028ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 21.781m | 5.520ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 6.004m | 3.635ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 9.864m | 5.113ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 8.072m | 5.339ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 9.239m | 5.528ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 28.359m | 12.392ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.386m | 5.197ms | 98 | 100 | 98.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 6.677m | 4.093ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 12.194m | 4.161ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.168h | 19.146ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 33.240m | 10.651ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 33.607m | 10.839ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 33.345m | 11.704ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 11.881m | 5.639ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 48 | 51 | 94.12 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.232m | 3.758ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 15.462m | 5.972ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.234m | 3.109ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.016h | 17.780ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 19.914m | 5.306ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 15.029m | 4.585ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 9.456m | 3.859ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 10.765m | 5.767ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.720m | 3.751ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.589m | 2.728ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_write_clear | 7.662m | 2.773ms | 3 | 3 | 100.00 | ||
| TOTAL | 1034 | 2951 | 35.04 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 11 | 100.00 |
| V1 | 18 | 18 | 12 | 66.67 |
| V2 | 285 | 270 | 247 | 86.67 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 22 | 24.44 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 85.60 | 88.40 | 77.09 | 90.05 | -- | 89.40 | 83.77 | 84.87 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
Test chip_csr_bit_bash has 3 failures.
0.chip_csr_bit_bash.51810508746031565858127146152465723262205344209164442372262065226125692554370
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
2.chip_csr_bit_bash.69038270201068756638697238363644192148298488138947332690983212004343657726529
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
... and 1 more failures.
Test chip_same_csr_outstanding has 3 failures.
0.chip_same_csr_outstanding.15359239452930512201847971792640726772802629716013573979498192288111929987716
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
2.chip_same_csr_outstanding.69669685874310221677352852331436412698035128091951770711328401411908833353242
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
... and 1 more failures.
Test chip_prim_tl_access has 2 failures.
0.chip_prim_tl_access.108946649874571818733109680901788496589521834067309745641004943388033443028534
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
2.chip_prim_tl_access.90330601680837195081409824417795019745830199485537999381346174650367499256281
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
Test xbar_smoke has 8 failures.
0.xbar_smoke.12459253364021710434375764524056802861958575747483951991500696473598435430500
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
2.xbar_smoke.61275935238038985076525478970874673419253057609441080142405984537992996304403
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
... and 6 more failures.
Test xbar_smoke_large_delays has 8 failures.
0.xbar_smoke_large_delays.53857425488650211354595475194295454868136026640029018591041179257390422571008
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
2.xbar_smoke_large_delays.36007659931841910485129141209900227857811633977173264352823214663473428342120
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
Test chip_csr_aliasing has 3 failures.
0.chip_csr_aliasing.85345055228510146390349927615952851342569001899297273643226774568459493142726
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
2.chip_csr_aliasing.51991796475727489491810611917091087247235858236103269101359534831898986648677
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
... and 1 more failures.
Test chip_tl_errors has 8 failures.
0.chip_tl_errors.38264453602243226364695464724880092166460708536160780856956757229503676730481
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
2.chip_tl_errors.57875753652258600801447099330147692907520564011384041935196826120219141157819
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
... and 6 more failures.
Test chip_rv_dm_lc_disabled has 2 failures.
0.chip_rv_dm_lc_disabled.63414390954456530230614326161427583231383887349906134446206342046507439715380
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
2.chip_rv_dm_lc_disabled.53887102955904463406370594181620425011453340814716939962949398871560850469413
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
Test xbar_smoke_zero_delays has 8 failures.
0.xbar_smoke_zero_delays.59246528720225716518375674573377739020411025006808333875863372474026417253522
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
2.xbar_smoke_zero_delays.70532148914759042541571829070579326245166353384847752358159100149957364148974
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
... and 6 more failures.
Test xbar_smoke_slow_rsp has 8 failures.
0.xbar_smoke_slow_rsp.57591673611995760271656157212239140344131881556462921877967810146615965997649
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
2.xbar_smoke_slow_rsp.28853831213514261494910553606060920055085684088989789734134860278601684040999
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
0.chip_sw_rv_timer_systick_test.55077678916020955910438208619767812295841240921037829911298175407045081578667
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:d815e9cc-5bc8-487c-a924-7ef8cfd90ad1
1.chip_sw_rv_timer_systick_test.30753898545811210670993306730928728085195003186558263491250337194239534171172
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:a98f182e-37a4-47df-9fad-de5f0608365a
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
9.chip_sw_all_escalation_resets.20647341982738609418731280442983271623126926765136183532447365758774526418029
Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3518.994896 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3518.994896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.chip_sw_all_escalation_resets.34893957207313754209841762223617628741669953621349717466230314198611930620248
Line 827, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2768.870120 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2768.870120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
6.chip_sw_alert_handler_lpg_sleep_mode_alerts.113529156897016993957030129934412651445932952472707105264143157834823313138766
Line 842, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4251.259848 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 4251.259848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---