Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3494922	1			T78	1159		T79	111		T80	2347
values[2]	704057	1			T78	330		T79	27		T80	195
values[3]	102230	1			T78	1		T79	2		T82	2
values[4]	54932	1			T79	1		T442	47		T513	210
values[5]	36857	1			T442	47		T513	92		T504	335
values[6]	27580	1			T442	19		T513	27		T504	216
values[7]	22370	1			T442	13		T513	33		T504	188
values[8]	18960	1			T442	4		T513	20		T504	181
values[9]	16485	1			T513	18		T504	112		T433	70
values[10]	15310	1			T513	19		T504	94		T433	59
values[11]	13823	1			T513	19		T504	68		T433	49
values[12]	13246	1			T513	16		T504	53		T433	37
values[13]	12542	1			T513	13		T504	57		T433	24
values[14]	11765	1			T513	10		T504	46		T433	18
values[15]	11413	1			T513	9		T504	28		T433	19
values[16]	11103	1			T513	9		T504	27		T433	20
values[17]	10391	1			T513	10		T504	17		T433	13
values[18]	10232	1			T513	14		T504	9		T433	12
values[19]	9898	1			T513	10		T504	7		T433	9
values[20]	9531	1			T513	13		T504	7		T433	11
values[21]	9348	1			T513	10		T504	11		T433	24
values[22]	9130	1			T513	7		T504	8		T433	43
values[23]	8636	1			T513	13		T504	10		T433	37
values[24]	8281	1			T513	14		T504	16		T433	10
values[25]	7902	1			T513	9		T504	7		T433	26
values[26]	7865	1			T513	9		T504	11		T433	17
values[27]	7701	1			T513	12		T504	12		T433	6
values[28]	7267	1			T513	20		T504	12		T433	4
values[29]	6708	1			T513	16		T504	9		T433	5
values[30]	6219	1			T513	12		T504	8		T433	5
values[31]	5767	1			T513	8		T504	8		T433	9
values[32]	5497	1			T513	7		T504	8		T433	13
values[33]	5092	1			T513	8		T504	15		T433	16
values[34]	4806	1			T513	10		T504	15		T433	10
values[35]	4310	1			T513	10		T504	13		T433	6
values[36]	4029	1			T513	8		T504	9		T433	4
values[37]	3798	1			T513	9		T504	11		T433	10
values[38]	3586	1			T513	15		T504	11		T433	10
values[39]	3422	1			T513	12		T504	14		T433	2
values[40]	3416	1			T513	8		T504	9		T433	2
values[41]	3367	1			T513	6		T504	6		T433	5
values[42]	3243	1			T513	12		T504	7		T433	2
values[43]	3245	1			T513	12		T504	8		T433	4
values[44]	3092	1			T513	12		T504	5		T433	5
values[45]	3003	1			T513	8		T504	6		T433	8
values[46]	2937	1			T513	10		T504	15		T433	3
values[47]	2865	1			T513	12		T504	8		T433	6
values[48]	2947	1			T513	9		T504	8		T433	7
values[49]	2903	1			T513	12		T504	10		T433	1
values[50]	2855	1			T513	10		T504	7		T433	1
values[51]	2735	1			T513	13		T504	8		T433	4
values[52]	2644	1			T513	6		T504	5		T433	1
values[53]	2657	1			T513	5		T504	4		T810	8
values[54]	2602	1			T513	10		T504	7		T810	9
values[55]	2523	1			T513	9		T504	8		T810	8
values[56]	2538	1			T513	14		T504	6		T810	8
values[57]	2413	1			T513	7		T504	5		T810	8
values[58]	2343	1			T513	9		T504	8		T810	9
values[59]	2331	1			T513	8		T504	15		T810	8
values[60]	2349	1			T513	8		T504	17		T810	8
values[61]	2516	1			T513	17		T504	9		T810	8
values[62]	3721	1			T513	52		T504	22		T810	8
values[63]	9734	1			T513	112		T504	52		T810	10
values[64]	226658	1			T513	277		T504	150		T810	1476

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4506439	1			T78	1177		T79	127		T80	2664
values[2]	770074	1			T78	332		T79	39		T80	160
values[3]	82691	1			T78	8		T79	9		T80	2
values[4]	14758	1			T79	2		T389	1		T442	8
values[5]	5515	1			T79	1		T442	2		T513	67
values[6]	3411	1			T513	46		T504	3		T521	1
values[7]	2515	1			T513	17		T504	2		T810	2
values[8]	2027	1			T513	2		T504	5		T810	1
values[9]	1851	1			T504	8		T810	1		T421	2
values[10]	1741	1			T504	6		T810	1		T421	2
values[11]	1546	1			T504	2		T810	1		T421	2
values[12]	1414	1			T504	2		T810	1		T421	2
values[13]	1190	1			T504	9		T810	1		T421	3
values[14]	1075	1			T504	15		T810	1		T421	2
values[15]	1058	1			T504	13		T810	1		T421	2
values[16]	1125	1			T504	9		T810	1		T421	2
values[17]	1042	1			T504	5		T810	1		T421	2
values[18]	936	1			T504	3		T810	1		T421	2
values[19]	914	1			T504	2		T810	1		T421	2
values[20]	860	1			T504	6		T810	1		T421	2
values[21]	814	1			T504	6		T810	1		T421	2
values[22]	795	1			T504	2		T810	1		T421	2
values[23]	734	1			T504	1		T810	1		T421	2
values[24]	674	1			T504	5		T810	1		T421	2
values[25]	679	1			T504	1		T810	1		T421	2
values[26]	690	1			T504	3		T810	1		T421	2
values[27]	602	1			T504	3		T810	1		T421	2
values[28]	605	1			T504	1		T810	1		T421	3
values[29]	562	1			T504	1		T810	1		T421	2
values[30]	524	1			T504	1		T810	1		T421	2
values[31]	554	1			T504	1		T810	1		T421	2
values[32]	504	1			T504	1		T810	1		T421	1
values[33]	494	1			T504	3		T810	1		T421	1
values[34]	494	1			T504	2		T810	1		T421	3
values[35]	480	1			T504	1		T810	1		T421	2
values[36]	499	1			T504	3		T810	1		T421	2
values[37]	524	1			T504	4		T810	1		T421	2
values[38]	510	1			T504	5		T810	1		T421	2
values[39]	464	1			T504	7		T810	1		T421	2
values[40]	432	1			T504	7		T810	1		T421	2
values[41]	419	1			T504	6		T810	1		T421	2
values[42]	400	1			T504	4		T810	1		T421	2
values[43]	408	1			T504	3		T810	1		T421	2
values[44]	469	1			T504	14		T810	1		T421	2
values[45]	420	1			T504	2		T810	1		T421	2
values[46]	394	1			T504	1		T810	1		T421	2
values[47]	372	1			T504	1		T810	1		T421	2
values[48]	348	1			T504	2		T810	1		T421	2
values[49]	341	1			T504	4		T810	1		T421	2
values[50]	348	1			T504	3		T810	1		T421	2
values[51]	330	1			T504	6		T810	1		T421	2
values[52]	333	1			T504	5		T810	1		T421	2
values[53]	347	1			T810	1		T421	2		T895	1
values[54]	344	1			T810	1		T421	2		T895	1
values[55]	329	1			T810	1		T421	2		T895	1
values[56]	321	1			T810	1		T421	2		T895	1
values[57]	334	1			T810	1		T421	2		T895	1
values[58]	300	1			T810	1		T421	2		T895	1
values[59]	319	1			T810	1		T421	2		T895	1
values[60]	318	1			T810	1		T421	2		T895	1
values[61]	337	1			T810	1		T421	2		T895	1
values[62]	525	1			T810	1		T421	2		T895	1
values[63]	1818	1			T810	1		T421	4		T895	1
values[64]	23710	1			T810	200		T421	108		T895	219

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	558418	1			T78	10		T79	1		T80	20
values[2]	2467112	1			T78	1137		T79	138		T80	2576
values[3]	1110709	1			T78	337		T79	47		T80	220
values[4]	143575	1			T79	4		T82	3		T210	10
values[5]	73305	1			T442	285		T513	342		T504	759
values[6]	47510	1			T442	202		T513	204		T504	518
values[7]	34709	1			T442	87		T513	90		T504	415
values[8]	27834	1			T442	73		T513	58		T504	275
values[9]	23721	1			T442	78		T513	41		T504	194
values[10]	20173	1			T442	56		T513	25		T504	152
values[11]	17661	1			T442	32		T513	26		T504	103
values[12]	16193	1			T442	26		T513	14		T504	85
values[13]	15284	1			T442	21		T513	24		T504	116
values[14]	14568	1			T442	25		T513	29		T504	139
values[15]	13690	1			T442	27		T513	22		T504	146
values[16]	12959	1			T442	26		T513	26		T504	113
values[17]	12464	1			T442	28		T513	19		T504	72
values[18]	11932	1			T442	22		T513	13		T504	62
values[19]	11559	1			T442	18		T513	12		T504	54
values[20]	10963	1			T442	18		T513	10		T504	28
values[21]	10493	1			T442	15		T513	10		T504	19
values[22]	10581	1			T442	26		T513	33		T504	11
values[23]	10162	1			T442	28		T513	24		T504	15
values[24]	9588	1			T442	17		T513	21		T504	11
values[25]	9298	1			T442	10		T513	19		T504	10
values[26]	8843	1			T442	14		T513	12		T504	12
values[27]	8356	1			T442	24		T513	22		T504	11
values[28]	8140	1			T442	12		T513	16		T504	3
values[29]	7769	1			T442	19		T513	17		T504	5
values[30]	7259	1			T442	20		T513	18		T504	11
values[31]	6526	1			T442	6		T513	16		T504	10
values[32]	5949	1			T442	6		T513	17		T504	18
values[33]	5552	1			T442	4		T513	20		T504	12
values[34]	5279	1			T442	4		T513	17		T504	14
values[35]	5026	1			T442	4		T513	20		T504	12
values[36]	4578	1			T442	9		T513	17		T504	10
values[37]	4360	1			T442	2		T513	14		T504	8
values[38]	4097	1			T442	6		T513	10		T504	6
values[39]	3961	1			T442	3		T513	7		T504	5
values[40]	3731	1			T442	6		T513	16		T504	5
values[41]	3657	1			T442	2		T513	26		T504	10
values[42]	3586	1			T442	1		T513	23		T504	13
values[43]	3536	1			T442	3		T513	8		T504	10
values[44]	3321	1			T442	2		T513	11		T504	15
values[45]	3255	1			T442	1		T513	10		T504	9
values[46]	3211	1			T442	2		T513	13		T504	10
values[47]	3180	1			T442	1		T513	15		T504	4
values[48]	3142	1			T442	2		T513	18		T504	6
values[49]	3054	1			T442	2		T513	9		T504	9
values[50]	2948	1			T442	7		T513	12		T504	9
values[51]	2983	1			T442	3		T513	17		T504	19
values[52]	2997	1			T442	1		T513	17		T504	9
values[53]	3046	1			T442	9		T513	19		T504	6
values[54]	2905	1			T442	3		T513	15		T504	8
values[55]	2800	1			T442	2		T513	16		T504	5
values[56]	2731	1			T442	2		T513	9		T504	5
values[57]	2723	1			T442	1		T513	6		T504	3
values[58]	2622	1			T442	3		T513	5		T504	7
values[59]	2537	1			T442	3		T513	8		T504	6
values[60]	2509	1			T442	3		T513	9		T504	6
values[61]	2676	1			T442	4		T513	8		T504	5
values[62]	3509	1			T442	3		T513	22		T504	16
values[63]	8492	1			T442	11		T513	57		T504	23
values[64]	219680	1			T442	99		T513	159		T504	76