Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2036651	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37720322

1

T1

3851

T2

12921

T3

11737

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27790797	1			T1	1091		T2	5173		T3	5179
values[0x0]	10460342	1			T1	2760		T2	7748		T3	6558
values[0x1]	1505834	1			T1	153		T2	866		T3	675

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	679815	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39077158

1

T1

4004

T2

13787

T3

12412

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18684464	1			T1	2002		T2	6894		T3	6206
valid_sources[0x01]	18683609	1			T1	2002		T2	6893		T3	6206
valid_sources[0x02]	38998	1			T203	5		T382	222		T956	10
valid_sources[0x03]	38955	1			T50	1		T52	1		T382	217
valid_sources[0x04]	38332	1			T52	2		T382	198		T956	6
valid_sources[0x05]	38292	1			T50	2		T382	211		T956	3
valid_sources[0x06]	38881	1			T50	1		T52	1		T382	256
valid_sources[0x07]	38285	1			T382	275		T956	5		T146	534
valid_sources[0x08]	38420	1			T50	1		T203	1		T382	277
valid_sources[0x09]	39439	1			T382	227		T956	15		T146	395
valid_sources[0x0a]	37793	1			T50	1		T52	1		T382	273
valid_sources[0x0b]	38430	1			T382	269		T956	1		T146	401
valid_sources[0x0c]	39159	1			T50	1		T52	2		T203	3
valid_sources[0x0d]	38854	1			T52	1		T203	1		T382	257
valid_sources[0x0e]	38248	1			T50	1		T382	246		T956	2
valid_sources[0x0f]	38195	1			T50	1		T382	300		T956	11
valid_sources[0x10]	37955	1			T382	236		T956	16		T146	366
valid_sources[0x11]	38221	1			T382	224		T956	11		T146	350
valid_sources[0x12]	38680	1			T50	1		T52	1		T382	291
valid_sources[0x13]	38366	1			T50	1		T382	252		T956	8
valid_sources[0x14]	38718	1			T50	3		T52	2		T382	232
valid_sources[0x15]	38043	1			T382	258		T956	14		T146	376
valid_sources[0x16]	39320	1			T50	1		T52	1		T382	264
valid_sources[0x17]	38843	1			T52	2		T382	227		T956	13
valid_sources[0x18]	38585	1			T382	250		T956	15		T146	417
valid_sources[0x19]	38415	1			T382	245		T956	9		T146	319
valid_sources[0x1a]	38314	1			T50	2		T382	295		T956	4
valid_sources[0x1b]	38781	1			T50	1		T81	39		T382	212
valid_sources[0x1c]	39200	1			T203	4		T382	303		T956	7
valid_sources[0x1d]	38233	1			T50	1		T382	217		T956	10
valid_sources[0x1e]	38868	1			T50	1		T204	39		T382	279
valid_sources[0x1f]	38729	1			T52	2		T382	284		T956	7
valid_sources[0x20]	38063	1			T382	206		T956	12		T146	422

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27063185

1

T1

1091

T2

5173

T3

5179

values[0x0]

all_enables

biggest_size

10397587

1

T1

2760

T2

7748

T3

6558

values[0x1]

all_enables

biggest_size

259550

1

T50

17

T52

21

T81

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2697627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

426769

1

T78

199

T79

17

T80

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1059019	1			T78	471		T79	49		T80	52
values[0x0]	1007059	1			T78	497		T79	40		T80	7
values[0x1]	1058318	1			T78	522		T79	52		T80	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2088661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1035735

1

T78

491

T79

52

T80

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48616	1			T78	35		T79	2		T80	1
valid_sources[0x01]	49963	1			T78	33		T79	3		T80	4
valid_sources[0x02]	48614	1			T78	25		T79	2		T80	2
valid_sources[0x03]	48277	1			T78	45		T79	2		T80	1
valid_sources[0x04]	48723	1			T78	28		T79	2		T80	1
valid_sources[0x05]	48817	1			T78	29		T79	2		T80	5
valid_sources[0x06]	48431	1			T78	13		T79	1		T80	1
valid_sources[0x07]	49128	1			T78	41		T79	4		T80	2
valid_sources[0x08]	49285	1			T78	12		T79	4		T80	4
valid_sources[0x09]	48766	1			T78	23		T79	3		T80	2
valid_sources[0x0a]	49505	1			T78	17		T79	4		T80	3
valid_sources[0x0b]	49847	1			T78	53		T79	5		T80	2
valid_sources[0x0c]	48737	1			T78	17		T79	2		T80	4
valid_sources[0x0d]	48724	1			T78	27		T79	3		T80	3
valid_sources[0x0e]	48554	1			T78	25		T79	2		T82	1
valid_sources[0x0f]	48767	1			T78	12		T79	2		T80	1
valid_sources[0x10]	49051	1			T78	29		T79	2		T80	5
valid_sources[0x11]	48371	1			T78	9		T79	1		T80	1
valid_sources[0x12]	49281	1			T78	43		T79	1		T82	2
valid_sources[0x13]	49372	1			T78	16		T79	4		T80	3
valid_sources[0x14]	48037	1			T78	4		T79	3		T80	1
valid_sources[0x15]	49953	1			T78	16		T80	1		T210	1
valid_sources[0x16]	48338	1			T78	26		T79	3		T389	13
valid_sources[0x17]	49092	1			T78	4		T79	1		T80	3
valid_sources[0x18]	48890	1			T78	23		T79	1		T80	1
valid_sources[0x19]	48945	1			T78	89		T79	3		T80	1
valid_sources[0x1a]	49372	1			T78	20		T79	4		T80	3
valid_sources[0x1b]	48527	1			T78	30		T79	4		T80	1
valid_sources[0x1c]	48509	1			T79	3		T80	3		T82	2
valid_sources[0x1d]	49781	1			T78	24		T79	2		T80	1
valid_sources[0x1e]	47744	1			T78	27		T79	1		T80	1
valid_sources[0x1f]	47381	1			T78	3		T79	2		T80	5
valid_sources[0x20]	48611	1			T78	39		T79	2		T80	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44675

1

T78

20

T79

3

T80

5

values[0x0]

all_enables

biggest_size

337048

1

T78

154

T79

13

T80

6

values[0x1]

all_enables

biggest_size

45046

1

T78

25

T79

1

T80

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2874937	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

468384

1

T78

219

T79

28

T80

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1144323	1			T78	550		T79	59		T80	63
values[0x0]	1053216	1			T78	504		T79	50		T80	10
values[0x1]	1145782	1			T78	463		T79	69		T80	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2206940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1136381

1

T78

508

T79

63

T80

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52152	1			T78	36		T79	5		T82	1
valid_sources[0x01]	52317	1			T78	11		T80	2		T210	6
valid_sources[0x02]	52199	1			T78	73		T79	1		T80	3
valid_sources[0x03]	51905	1			T78	2		T79	4		T82	8
valid_sources[0x04]	52438	1			T78	35		T79	3		T80	2
valid_sources[0x05]	52265	1			T78	6		T79	2		T80	2
valid_sources[0x06]	51667	1			T78	21		T79	4		T80	4
valid_sources[0x07]	53301	1			T78	20		T79	5		T82	1
valid_sources[0x08]	52709	1			T78	18		T79	4		T80	1
valid_sources[0x09]	50769	1			T78	33		T79	4		T80	3
valid_sources[0x0a]	53528	1			T78	15		T79	3		T80	1
valid_sources[0x0b]	52517	1			T78	20		T79	2		T82	3
valid_sources[0x0c]	52652	1			T78	2		T79	2		T80	1
valid_sources[0x0d]	51704	1			T78	16		T79	5		T80	2
valid_sources[0x0e]	51996	1			T78	29		T79	3		T82	3
valid_sources[0x0f]	52987	1			T78	11		T79	3		T80	2
valid_sources[0x10]	52447	1			T78	29		T79	1		T80	7
valid_sources[0x11]	53628	1			T78	10		T79	6		T80	2
valid_sources[0x12]	52392	1			T78	33		T79	4		T82	2
valid_sources[0x13]	51672	1			T78	41		T80	8		T82	1
valid_sources[0x14]	51674	1			T78	26		T79	2		T82	2
valid_sources[0x15]	52053	1			T78	36		T79	3		T80	5
valid_sources[0x16]	51926	1			T78	13		T79	6		T82	4
valid_sources[0x17]	52623	1			T78	22		T79	2		T210	6
valid_sources[0x18]	52671	1			T78	28		T79	3		T82	2
valid_sources[0x19]	52696	1			T78	22		T79	3		T80	4
valid_sources[0x1a]	51882	1			T78	7		T79	4		T80	2
valid_sources[0x1b]	51563	1			T78	37		T80	3		T82	5
valid_sources[0x1c]	52480	1			T78	30		T79	5		T80	2
valid_sources[0x1d]	51985	1			T78	13		T79	3		T82	4
valid_sources[0x1e]	52174	1			T78	15		T79	4		T80	3
valid_sources[0x1f]	51531	1			T78	36		T79	2		T80	5
valid_sources[0x20]	51966	1			T78	14		T79	3		T80	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49026

1

T78

19

T79

2

T80

5

values[0x0]

all_enables

biggest_size

370291

1

T78

183

T79

21

T80

5

values[0x1]

all_enables

biggest_size

49067

1

T78

17

T79

5

T80

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2723764	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

430332

1

T78

223

T79

20

T80

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1068044	1			T78	466		T79	66		T80	55
values[0x0]	1018392	1			T78	514		T79	59		T80	11
values[0x1]	1067660	1			T78	504		T79	65		T80	66

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2108601	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1045495

1

T78

503

T79

65

T80

50

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48776	1			T78	23		T80	1		T82	5
valid_sources[0x01]	49431	1			T78	24		T80	2		T82	1
valid_sources[0x02]	48910	1			T78	29		T80	3		T82	1
valid_sources[0x03]	48636	1			T78	23		T80	3		T82	1
valid_sources[0x04]	49394	1			T78	42		T80	3		T82	2
valid_sources[0x05]	49472	1			T78	50		T82	3		T210	5
valid_sources[0x06]	48892	1			T78	46		T79	11		T80	3
valid_sources[0x07]	48871	1			T78	27		T80	1		T210	1
valid_sources[0x08]	49954	1			T78	14		T79	25		T82	2
valid_sources[0x09]	49088	1			T78	42		T80	3		T82	2
valid_sources[0x0a]	48957	1			T78	6		T80	7		T82	1
valid_sources[0x0b]	49481	1			T78	36		T80	2		T82	1
valid_sources[0x0c]	49344	1			T78	33		T80	3		T82	2
valid_sources[0x0d]	48940	1			T78	44		T79	10		T80	2
valid_sources[0x0e]	50036	1			T78	26		T80	3		T82	4
valid_sources[0x0f]	49597	1			T80	2		T82	1		T210	3
valid_sources[0x10]	49446	1			T78	8		T79	3		T80	1
valid_sources[0x11]	49110	1			T78	25		T82	2		T210	1
valid_sources[0x12]	49127	1			T78	4		T82	3		T210	2
valid_sources[0x13]	49257	1			T78	21		T82	2		T210	1
valid_sources[0x14]	49319	1			T78	10		T80	1		T82	1
valid_sources[0x15]	49756	1			T78	18		T80	9		T82	2
valid_sources[0x16]	49955	1			T78	8		T79	3		T80	1
valid_sources[0x17]	49737	1			T78	8		T79	10		T80	1
valid_sources[0x18]	49195	1			T78	23		T79	16		T80	1
valid_sources[0x19]	50230	1			T78	1		T80	3		T82	3
valid_sources[0x1a]	49256	1			T78	7		T80	2		T82	3
valid_sources[0x1b]	49609	1			T78	31		T79	3		T80	2
valid_sources[0x1c]	49076	1			T78	13		T80	2		T82	1
valid_sources[0x1d]	49300	1			T78	36		T79	5		T82	2
valid_sources[0x1e]	48386	1			T78	12		T79	2		T80	1
valid_sources[0x1f]	48337	1			T78	18		T79	5		T82	5
valid_sources[0x20]	49145	1			T78	25		T79	2		T80	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45537

1

T78

26

T79

3

T80

3

values[0x0]

all_enables

biggest_size

339637

1

T78

174

T79

14

T80

5

values[0x1]

all_enables

biggest_size

45158

1

T78

23

T79

3

T80

5