Unified Coverage Report :: Module :: pinmux_wkup

Module : pinmux_wkup

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.33	78.95	92.31			72.73

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup	45.52	52.63	38.46			45.45
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup	56.72	63.16	61.54			45.45
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup	59.28	63.16	69.23			45.45
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup	59.28	63.16	69.23			45.45
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup	64.07	68.42	69.23			54.55
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup	64.07	68.42	69.23			54.55
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup	64.07	68.42	69.23			54.55
tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup	81.33	78.95	92.31			72.73

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
45.52	52.63	38.46			45.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.14	63.89	40.91			63.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	99.03	89.42	98.84		86.38	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	67.58	76.47	44.44			81.82

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.72	63.16	61.54			45.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.85	80.56	77.27			72.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	99.03	89.42	98.84		86.38	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.28	63.16	69.23			45.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.37	80.56	81.82			72.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	99.03	89.42	98.84		86.38	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.28	63.16	69.23			45.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.34	80.56	77.27			68.18

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	99.03	89.42	98.84		86.38	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	93.27	100.00	88.89			90.91

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.07	68.42	69.23			54.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.81	83.33	81.82			77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	99.03	89.42	98.84		86.38	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.07	68.42	69.23			54.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.81	83.33	81.82			77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	99.03	89.42	98.84		86.38	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.07	68.42	69.23			54.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.81	83.33	81.82			77.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	99.03	89.42	98.84		86.38	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.33	78.95	92.31			72.73

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.24	88.89	95.45			86.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.13	99.03	89.42	98.84		86.38	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_filter	100.00	100.00	100.00			100.00

Line Coverage for Module : pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	6	60.00
ALWAYS	82	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
50	1	1
52	1	1
55	1	1
56	1	1
57	1	1
58	1	1
60	1	1
63	1	1
66	0	1
67	0	1
70	0	1
71	0	1
			MISSING_ELSE
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1

---

Cond Coverage for Module : pinmux_wkup

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T16,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T50,T16,T18

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T16,T18
1	1	Covered	T50,T16,T18

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T50,T52,T53
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T50,T52,T53
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T54,T55,T56
0	1	Covered	T54,T55,T56
1	0	Covered	T54,T56

---

Branch Coverage for Module : pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	8	72.73
TERNARY	50	3	2	66.67
IF	57	6	4	66.67
IF	82	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(cnt_eq_th) ? 
-2-:	50	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T50,T52,T53

	LineNo.	Expression
-1-:	57	if (wkup_en_i)
-2-:	58	case (wkup_mode_i)

Branches:

-1-	-2-	Status	Tests
1	Negedge	Covered	T54,T55,T56
1	Edge	Covered	T54,T55,T56
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T16,T18,T27
0	-	Covered	T50,T52,T53

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	10	52.63
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	3	30.00
ALWAYS	82	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
50	1	1
52	1	1
55	1	1
56	1	1
57	1	1
58	0	1
60	0	1
63	0	1
66	0	1
67	0	1
70	0	1
71	0	1
			MISSING_ELSE
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	5	38.46
Logical	13	5	38.46
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T52,T53,T57
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T52,T53,T57
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[1].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	5	45.45
TERNARY	50	3	2	66.67
IF	57	6	1	16.67
IF	82	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(cnt_eq_th) ? 
-2-:	50	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T52,T53,T57

	LineNo.	Expression
-1-:	57	if (wkup_en_i)
-2-:	58	case (wkup_mode_i)

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Not Covered
0	-	Covered	T52,T53,T57

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	12	63.16
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	3	30.00
ALWAYS	82	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
50	1	1
52	1	1
55	1	1
56	1	1
57	1	1
58	0	1
60	0	1
63	0	1
66	0	1
67	0	1
70	0	1
71	0	1
			MISSING_ELSE
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	8	61.54
Logical	13	8	61.54
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50
1	1	Covered	T50

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T50,T52,T58
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T50,T52,T58
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[2].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	5	45.45
TERNARY	50	3	2	66.67
IF	57	6	1	16.67
IF	82	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(cnt_eq_th) ? 
-2-:	50	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	57	if (wkup_en_i)
-2-:	58	case (wkup_mode_i)

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Not Covered
0	-	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	12	63.16
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	3	30.00
ALWAYS	82	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
50	1	1
52	1	1
55	1	1
56	1	1
57	1	1
58	0	1
60	0	1
63	0	1
66	0	1
67	0	1
70	0	1
71	0	1
			MISSING_ELSE
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T52
1	0	Covered	T1,T2,T3
1	1	Covered	T52

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52
1	1	Covered	T52

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T50,T52
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T50,T52
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[4].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	5	45.45
TERNARY	50	3	2	66.67
IF	57	6	1	16.67
IF	82	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(cnt_eq_th) ? 
-2-:	50	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T50,T52

	LineNo.	Expression
-1-:	57	if (wkup_en_i)
-2-:	58	case (wkup_mode_i)

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Not Covered
0	-	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	12	63.16
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	3	30.00
ALWAYS	82	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
50	1	1
52	1	1
55	1	1
56	1	1
57	1	1
58	0	1
60	0	1
63	0	1
66	0	1
67	0	1
70	0	1
71	0	1
			MISSING_ELSE
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T50,T52

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T52
1	1	Covered	T50,T52

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T50,T52,T58
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T50,T52,T58
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[6].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	5	45.45
TERNARY	50	3	2	66.67
IF	57	6	1	16.67
IF	82	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(cnt_eq_th) ? 
-2-:	50	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	57	if (wkup_en_i)
-2-:	58	case (wkup_mode_i)

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Not Covered
0	-	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	13	68.42
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	4	40.00
ALWAYS	82	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
50	1	1
52	1	1
55	1	1
56	1	1
57	1	1
58	1	1
60	0	1
63	0	1
66	0	1
67	0	1
70	0	1
71	0	1
			MISSING_ELSE
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T52,T59,T60
1	0	Covered	T1,T2,T3
1	1	Covered	T52

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T59,T60
1	1	Covered	T52,T59,T60

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T50,T58
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T50,T58
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[3].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	6	54.55
TERNARY	50	3	2	66.67
IF	57	6	2	33.33
IF	82	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(cnt_eq_th) ? 
-2-:	50	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T50,T58

	LineNo.	Expression
-1-:	57	if (wkup_en_i)
-2-:	58	case (wkup_mode_i)

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T59,T60
0	-	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	13	68.42
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	4	40.00
ALWAYS	82	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
50	1	1
52	1	1
55	1	1
56	1	1
57	1	1
58	1	1
60	0	1
63	0	1
66	0	1
67	0	1
70	0	1
71	0	1
			MISSING_ELSE
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T21,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T21,T61

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T21,T61
1	1	Covered	T18,T21,T61

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T52,T58
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T52,T58
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[5].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	6	54.55
TERNARY	50	3	2	66.67
IF	57	6	2	33.33
IF	82	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(cnt_eq_th) ? 
-2-:	50	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T52,T58

	LineNo.	Expression
-1-:	57	if (wkup_en_i)
-2-:	58	case (wkup_mode_i)

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T18,T21,T61
0	-	Covered	T52,T21,T62

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	13	68.42
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	4	40.00
ALWAYS	82	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
50	1	1
52	1	1
55	1	1
56	1	1
57	1	1
58	1	1
60	0	1
63	0	1
66	0	1
67	0	1
70	0	1
71	0	1
			MISSING_ELSE
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T52,T63
1	0	Covered	T1,T2,T3
1	1	Covered	T50,T52

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T52,T63
1	1	Covered	T50,T52,T63

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T50,T52,T58
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T50,T52,T58
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[7].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	6	54.55
TERNARY	50	3	2	66.67
IF	57	6	2	33.33
IF	82	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(cnt_eq_th) ? 
-2-:	50	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	57	if (wkup_en_i)
-2-:	58	case (wkup_mode_i)

Branches:

-1-	-2-	Status	Tests
1	Negedge	Not Covered
1	Edge	Not Covered
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T63
0	-	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	1	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
ALWAYS	55	10	6	60.00
ALWAYS	82	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
50	1	1
52	1	1
55	1	1
56	1	1
57	1	1
58	1	1
60	1	1
63	1	1
66	0	1
67	0	1
70	0	1
71	0	1
			MISSING_ELSE
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((~filter_out_d)) & filter_out_q)
             --------1--------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T27,T58
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T27,T58

 LINE       46
 EXPRESSION (filter_out_d & ((~filter_out_q)))
             ------1-----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T27,T58
1	1	Covered	T16,T27,T58

 LINE       50
 EXPRESSION (cnt_eq_th ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : '0))
             ----1----

-1-	Status	Tests
0	Covered	T50,T52,T58
1	Covered	T1,T2,T3

 LINE       50
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : '0)
                 ---1--

-1-	Status	Tests
0	Covered	T50,T52,T58
1	Not Covered

 LINE       63
 EXPRESSION (rising | falling)
             ---1--   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T54,T55,T56
0	1	Covered	T54,T55,T56
1	0	Covered	T54,T56

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_wkup_detect[0].u_pinmux_wkup

	Line No.	Total	Covered	Percent
Branches		11	8	72.73
TERNARY	50	3	2	66.67
IF	57	6	4	66.67
IF	82	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_wkup.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	50	(cnt_eq_th) ? 
-2-:	50	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	57	if (wkup_en_i)
-2-:	58	case (wkup_mode_i)

Branches:

-1-	-2-	Status	Tests
1	Negedge	Covered	T54,T55,T56
1	Edge	Covered	T54,T55,T56
1	HighTimed	Not Covered
1	LowTimed	Not Covered
1	default	Covered	T16,T27,T64
0	-	Covered	T50,T52,T58

	LineNo.	Expression
-1-:	82	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3