Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533703584	61808468	0	0
DepthKnown_A	533703584	533596214	0	0
RvalidKnown_A	533703584	533596214	0	0
WreadyKnown_A	533703584	533596214	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	61808468	0	0
T1	69381	7107	0	0
T2	226067	29713	0	0
T3	191090	22319	0	0
T4	390623	83030	0	0
T5	238308	23987	0	0
T6	196142	16249	0	0
T15	227328	23227	0	0
T90	81718	9106	0	0
T91	268469	21661	0	0
T92	241541	32401	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533703584	47704678	0	0
DepthKnown_A	533703584	533596214	0	0
RvalidKnown_A	533703584	533596214	0	0
WreadyKnown_A	533703584	533596214	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	47704678	0	0
T1	69381	5249	0	0
T2	226067	20051	0	0
T3	191090	17322	0	0
T4	390623	56014	0	0
T5	238308	17008	0	0
T6	196142	12483	0	0
T15	227328	19333	0	0
T90	81718	6732	0	0
T91	268469	17575	0	0
T92	241541	28130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533703584	44441172	0	0
DepthKnown_A	533703584	533596214	0	0
RvalidKnown_A	533703584	533596214	0	0
WreadyKnown_A	533703584	533596214	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	44441172	0	0
T1	69381	4120	0	0
T2	226067	14176	0	0
T3	191090	12760	0	0
T4	390623	99187	0	0
T5	238308	11551	0	0
T6	196142	9668	0	0
T15	227328	21592	0	0
T90	81718	4363	0	0
T91	268469	11055	0	0
T92	241541	13925	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533703584	37392351	0	0
DepthKnown_A	533703584	533596214	0	0
RvalidKnown_A	533703584	533596214	0	0
WreadyKnown_A	533703584	533596214	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	37392351	0	0
T1	69381	4004	0	0
T2	226067	13787	0	0
T3	191090	12412	0	0
T4	390623	98933	0	0
T5	238308	11191	0	0
T6	196142	9414	0	0
T15	227328	21388	0	0
T90	81718	4217	0	0
T91	268469	10312	0	0
T92	241541	13669	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	533596214	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621669737	86980	0	0
DepthKnown_A	621669737	621546014	0	0
RvalidKnown_A	621669737	621546014	0	0
WreadyKnown_A	621669737	621546014	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	86980	0	0
T1	69381	13	0	0
T2	226067	151	0	0
T3	191090	74	0	0
T4	390623	18	0	0
T5	238308	103	0	0
T6	196142	34	0	0
T15	227328	53	0	0
T90	81718	13	0	0
T91	268469	346	0	0
T92	241541	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621669737	89869	0	0
DepthKnown_A	621669737	621546014	0	0
RvalidKnown_A	621669737	621546014	0	0
WreadyKnown_A	621669737	621546014	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	89869	0	0
T1	69381	13	0	0
T2	226067	151	0	0
T3	191090	74	0	0
T4	390623	18	0	0
T5	238308	103	0	0
T6	196142	34	0	0
T15	227328	53	0	0
T90	81718	13	0	0
T91	268469	346	0	0
T92	241541	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621669737	53000	0	0
DepthKnown_A	621669737	621546014	0	0
RvalidKnown_A	621669737	621546014	0	0
WreadyKnown_A	621669737	621546014	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	53000	0	0
T1	69381	12	0	0
T2	226067	95	0	0
T3	191090	72	0	0
T4	390623	15	0	0
T5	238308	95	0	0
T6	196142	32	0	0
T15	227328	52	0	0
T90	81718	12	0	0
T91	268469	343	0	0
T92	241541	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621669737	53000	0	0
DepthKnown_A	621669737	621546014	0	0
RvalidKnown_A	621669737	621546014	0	0
WreadyKnown_A	621669737	621546014	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	53000	0	0
T1	69381	12	0	0
T2	226067	95	0	0
T3	191090	72	0	0
T4	390623	15	0	0
T5	238308	95	0	0
T6	196142	32	0	0
T15	227328	52	0	0
T90	81718	12	0	0
T91	268469	343	0	0
T92	241541	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621669737	33980	0	0
DepthKnown_A	621669737	621546014	0	0
RvalidKnown_A	621669737	621546014	0	0
WreadyKnown_A	621669737	621546014	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	33980	0	0
T1	69381	1	0	0
T2	226067	56	0	0
T3	191090	2	0	0
T4	390623	3	0	0
T5	238308	8	0	0
T6	196142	2	0	0
T15	227328	1	0	0
T90	81718	1	0	0
T91	268469	3	0	0
T92	241541	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	621669737	36869	0	0
DepthKnown_A	621669737	621546014	0	0
RvalidKnown_A	621669737	621546014	0	0
WreadyKnown_A	621669737	621546014	0	0
gen_passthru_fifo.paramCheckPass	2937	2937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	36869	0	0
T1	69381	1	0	0
T2	226067	56	0	0
T3	191090	2	0	0
T4	390623	3	0	0
T5	238308	8	0	0
T6	196142	2	0	0
T15	227328	1	0	0
T90	81718	1	0	0
T91	268469	3	0	0
T92	241541	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621669737	621546014	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2937	2937	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0