Unified Coverage Report :: Module

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00


Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T47,T149,T48	Yes	T47,T149,T48	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T47,T149,T48	Yes	T47,T149,T48	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T78,T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T50,T73,*T52	Yes	T50,T73,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T50,T52,T81	Yes	T50,T52,T81	INPUT
tl_i.a_valid	Yes	Yes	T47,T149,T48	Yes	T47,T149,T48	INPUT
tl_o.a_ready	Yes	Yes	T47,T149,T48	Yes	T47,T149,T48	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T47,T149,T48	Yes	T47,T149,T48	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T47,T149,T48	Yes	T47,T149,T48	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T47,T149,T48	Yes	T47,T149,T48	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T58,T780,*T775	Yes	T58,T780,T775	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T47,T149,*T48	Yes	T47,T149,T48	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T47,T149,T48	Yes	T47,T149,T48	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T292,T293,T516	Yes	T292,T293,T516	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T159	Yes	T83,T84,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T159	Yes	T83,T84,T159	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T292,T293,T516	Yes	T292,T293,T516	OUTPUT
cio_rx_i	Yes	Yes	T2,T5,T6	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T47,T149,T48	Yes	T47,T149,T48	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T149,T108,T216	Yes	T149,T108,T216	OUTPUT
intr_tx_empty_o	Yes	Yes	T149,T108,T216	Yes	T149,T108,T216	OUTPUT
intr_rx_watermark_o	Yes	Yes	T149,T108,T216	Yes	T149,T108,T216	OUTPUT
intr_tx_done_o	Yes	Yes	T149,T108,T216	Yes	T149,T108,T216	OUTPUT
intr_rx_overflow_o	Yes	Yes	T149,T108,T216	Yes	T149,T108,T216	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_break_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_timeout_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00


Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T47,T48,T108	Yes	T47,T48,T108	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T47,T48,T108	Yes	T47,T48,T108	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T78,T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T50,T73,*T52	Yes	T50,T73,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T50,T52,T81	Yes	T50,T52,T81	INPUT
tl_i.a_valid	Yes	Yes	T47,T48,T108	Yes	T47,T48,T108	INPUT
tl_o.a_ready	Yes	Yes	T47,T48,T108	Yes	T47,T48,T108	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T47,T48,T108	Yes	T47,T48,T108	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T47,T48,T108	Yes	T47,T48,T108	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T47,T48,T108	Yes	T47,T48,T108	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T80,T210	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T58,T780,*T775	Yes	T58,T780,T775	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T47,T48,*T108	Yes	T47,T48,T108	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T47,T48,T108	Yes	T47,T48,T108	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T83,T84,T65	Yes	T83,T84,T65	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T163	Yes	T83,T163,T241	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T163,T241	Yes	T83,T84,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T83,T84,T65	Yes	T83,T84,T65	OUTPUT
cio_rx_i	Yes	Yes	T2,T5,T6	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T47,T48,T108	Yes	T47,T48,T108	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T108,T216,T303	Yes	T108,T216,T303	OUTPUT
intr_tx_empty_o	Yes	Yes	T108,T216,T303	Yes	T108,T216,T303	OUTPUT
intr_rx_watermark_o	Yes	Yes	T108,T216,T303	Yes	T108,T216,T303	OUTPUT
intr_tx_done_o	Yes	Yes	T108,T216,T303	Yes	T108,T216,T303	OUTPUT
intr_rx_overflow_o	Yes	Yes	T108,T216,T303	Yes	T108,T216,T303	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_break_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_timeout_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00


Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T303,T214,T12	Yes	T303,T214,T12	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T303,T214,T12	Yes	T303,T214,T12	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T78,T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T50,T73,*T52	Yes	T50,T73,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T50,T52,T81	Yes	T50,T52,T81	INPUT
tl_i.a_valid	Yes	Yes	T303,T65,T214	Yes	T303,T65,T214	INPUT
tl_o.a_ready	Yes	Yes	T303,T65,T214	Yes	T303,T65,T214	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T303,T214,T12	Yes	T303,T214,T12	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T303,T214,T12	Yes	T303,T65,T214	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T303,T214,T12	Yes	T303,T65,T214	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T58,T78,*T79	Yes	T58,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T303,T214,*T12	Yes	T303,T214,T12	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T303,T65,T214	Yes	T303,T65,T214	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T292,T293,T83	Yes	T292,T293,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T159	Yes	T83,T84,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T159	Yes	T83,T84,T159	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T292,T293,T83	Yes	T292,T293,T83	OUTPUT
cio_rx_i	Yes	Yes	T35,T214,T334	Yes	T35,T214,T9	INPUT
cio_tx_o	Yes	Yes	T214,T334,T335	Yes	T214,T334,T335	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T303,T214,T334	Yes	T303,T214,T334	OUTPUT
intr_tx_empty_o	Yes	Yes	T303,T214,T334	Yes	T303,T214,T334	OUTPUT
intr_rx_watermark_o	Yes	Yes	T303,T214,T334	Yes	T303,T214,T334	OUTPUT
intr_tx_done_o	Yes	Yes	T303,T214,T334	Yes	T303,T214,T334	OUTPUT
intr_rx_overflow_o	Yes	Yes	T303,T214,T334	Yes	T303,T214,T334	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_break_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_timeout_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00


Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T78,T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T50,T73,*T52	Yes	T50,T73,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T50,T52,T81	Yes	T50,T52,T81	INPUT
tl_i.a_valid	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	INPUT
tl_o.a_ready	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T58,T78,*T79	Yes	T58,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T149,T316,*T328	Yes	T149,T316,T328	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T83,T84,T781	Yes	T83,T84,T781	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T83,T84,T781	Yes	T83,T84,T781	OUTPUT
cio_rx_i	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	INPUT
cio_tx_o	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
intr_tx_empty_o	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
intr_rx_watermark_o	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
intr_tx_done_o	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
intr_rx_overflow_o	Yes	Yes	T149,T316,T328	Yes	T149,T316,T328	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_break_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_timeout_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00


Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	T78,T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T50,T73,*T52	Yes	T50,T73,T52	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T50,T52,T81	Yes	T50,T52,T81	INPUT
tl_i.a_valid	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	INPUT
tl_o.a_ready	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
tl_o.d_error	Yes	Yes	T78,T80,T389	Yes	T78,T80,T389	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T58,T78,*T79	Yes	T58,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T80,T389	Yes	T78,T80,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T15,T303,*T314	Yes	T15,T303,T314	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T516,T83,T782	Yes	T516,T83,T782	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T163	Yes	T83,T84,T163	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T516,T83,T782	Yes	T516,T83,T782	OUTPUT
cio_rx_i	Yes	Yes	T15,T314,T205	Yes	T15,T314,T205	INPUT
cio_tx_o	Yes	Yes	T15,T314,T205	Yes	T15,T314,T205	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
intr_tx_empty_o	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
intr_rx_watermark_o	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
intr_tx_done_o	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
intr_rx_overflow_o	Yes	Yes	T15,T303,T314	Yes	T15,T303,T314	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_break_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_timeout_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T303,T317,T332	Yes	T303,T317,T332	OUTPUT

*Tests covering at least one bit in the range

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children