Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T79,T82,T210	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T79,T80,T210	Yes	T79,T80,T210	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T186,T217,T167	Yes	T186,T217,T167	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T186,T217,T167	Yes	T186,T217,T167	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T50,T52,T81	Yes	T50,T52,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T52,T81,T204	Yes	T52,T81,T204	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T52,T81,T204	Yes	T52,T81,T204	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T2,T69,T160	Yes	T2,T69,T160	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T50,T73,T74	Yes	T50,T73,T74	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T50,T73,T74	Yes	T50,T73,T74	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T50,T73,T74	Yes	T50,T73,T74	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T50,T73,T74	Yes	T50,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T50,T73,T74	Yes	T50,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T50,T74,T52	Yes	T50,T74,T52	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T50,*T73,*T74	Yes	T50,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T50,T73,T74	Yes	T50,T73,T74	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T50,*T52,*T58	Yes	T50,T52,T58	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T52,T78,T79	Yes	T52,T78,T79	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T50,*T52,*T58	Yes	T50,T52,T58	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T50,*T52,*T58	Yes	T50,T52,T58	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T50,T52,T257	Yes	T50,T52,T257	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T50,T52,T257	Yes	T50,T52,T257	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T50,T52,T257	Yes	T50,T52,T257	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T50,T52,T257	Yes	T50,T52,T257	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T50,T52,T257	Yes	T50,T52,T257	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T257,*T258,*T259	Yes	T257,T258,T259	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T50,T52,T257	Yes	T50,T52,T257	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T257,T258,T259	Yes	T257,T258,T259	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T50,T52,T257	Yes	T50,T52,T257	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T257,*T258,*T259	Yes	T257,T258,T259	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T3,T5	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T50,T52,T257	Yes	T50,T52,T257	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T47,T48,T73	Yes	T47,T48,T73	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T47,T48,T44	Yes	T47,T48,T44	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T50,T52,T65	Yes	T50,T52,T65	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T50,T52	Yes	T1,T50,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T50,T52	Yes	T1,T50,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T50,T52,T65	Yes	T50,T52,T65	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T1,T50,T52	Yes	T1,T50,T52	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T50,*T52,*T58	Yes	T50,T52,T58	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T1,T50,T52	Yes	T1,T50,T52	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T1,T50,T52	Yes	T1,T50,T52	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T78,T80,T82	Yes	T78,T80,T210	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T1,T397,T398	Yes	T1,T397,T398	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T50,T52,T58	Yes	T50,T52,T65	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T1,T50,T52	Yes	T1,T50,T52	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T50,*T52,*T58	Yes	T50,T52,T58	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T50,*T52,*T351	Yes	T1,T50,T52	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T1,T50,T52	Yes	T1,T50,T52	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T50,*T73,*T52	Yes	T50,T73,T52	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T50,T52,T81	Yes	T50,T52,T81	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T160,T248,T292	Yes	T160,T248,T292	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T50,*T73,*T52	Yes	T50,T73,T52	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T110,T156,T65	Yes	T110,T156,T65	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T110,T156,T65	Yes	T110,T156,T65	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T110,T156,T65	Yes	T110,T156,T65	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T110,T156,T65	Yes	T110,T156,T65	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T110,T156,T65	Yes	T110,T156,T65	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T110,T156,T65	Yes	T110,T156,T65	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T78,T80,T82	Yes	T78,T80,T82	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T13,T199,T95	Yes	T13,T199,T95	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T110,T156,T65	Yes	T110,T156,T65	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T110,T156,T65	Yes	T110,T156,T65	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T78,T80,T210	Yes	T78,T79,T80	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T110,T156,T383	Yes	T110,T156,T383	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T110,T156,T383	Yes	T110,T156,T65	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T110,T156,T383	Yes	T110,T156,T383	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T80,T82	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T78,T80,T82	Yes	T78,T80,T82	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T110,*T156,*T383	Yes	T110,T156,T383	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T110,T156,T65	Yes	T110,T156,T65	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T78,T80,T210	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T110,*T35,*T156	Yes	T110,T35,T156	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T110,T35,T156	Yes	T110,T35,T156	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T18,T303,T88	Yes	T18,T303,T88	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T18,T303,T19	Yes	T18,T303,T19	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T303,T88	Yes	T18,T303,T88	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T18,T303,T88	Yes	T18,T303,T88	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T18,T303,T19	Yes	T18,T303,T19	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T18,T303,T88	Yes	T18,T303,T88	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T58,*T78,*T79	Yes	T58,T78,T79	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T18,T303,T88	Yes	T18,T303,T88	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T18,T303,T88	Yes	T18,T303,T88	INPUT
tl_usbdev_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T303,T19,T383	Yes	T303,T88,T19	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T303,T88,T19	Yes	T303,T19,T383	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T18,T303,T88	Yes	T303,T19,T20	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T58,*T78,*T79	Yes	T58,T78,T79	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T18,*T303,*T19	Yes	T303,T19,T20	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T18,T303,T88	Yes	T18,T303,T88	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T78,T80,T82	Yes	T78,T80,T82	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T78,T80,T210	Yes	T78,T80,T210	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T79,T82,T210	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T80,T210	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T298,T369,T764	Yes	T298,T369,T764	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	INPUT
tl_hmac_i.d_error	Yes	Yes	T78,T80,T82	Yes	T78,T79,T80	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	INPUT
tl_hmac_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T80,T210	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T78,*T80,*T389	Yes	T78,T79,T80	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T80,T82	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T47,*T298,*T48	Yes	T47,T298,T48	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T47,T298,T48	Yes	T47,T298,T48	INPUT
tl_kmac_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T8,T310,T177	Yes	T8,T310,T177	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T154,T8,T310	Yes	T154,T8,T310	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T154,T8,T310	Yes	T154,T8,T310	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T8,T310,T177	Yes	T8,T310,T177	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T154,T8,T310	Yes	T154,T8,T310	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T52,*T78,*T79	Yes	T52,T78,T79	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T310,T411,T266	Yes	T310,T411,T266	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T154,T8,T310	Yes	T154,T8,T310	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T154,T8,T310	Yes	T154,T8,T310	INPUT
tl_kmac_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T154,T8,T310	Yes	T154,T8,T310	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T154,T8,T310	Yes	T154,T8,T310	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T154,T8,T310	Yes	T154,T8,T310	INPUT
tl_kmac_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T80,T210	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T52,*T78,*T79	Yes	T52,T78,T79	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T78,T80,T389	Yes	T78,T79,T80	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T154,*T8,*T310	Yes	T154,T8,T310	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T154,T8,T310	Yes	T154,T8,T310	INPUT
tl_aes_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	INPUT
tl_aes_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	INPUT
tl_aes_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T90,*T128,*T311	Yes	T90,T128,T311	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T90,T128,T311	Yes	T90,T128,T311	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T78,T80,T82	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T4,*T128,*T129	Yes	T4,T47,T128	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T80,T210	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T78,T80,T82	Yes	T78,T79,T80	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T78,*T80,*T389	Yes	T78,T79,T80	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T78,T80,T82	Yes	T78,T79,T80	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T4,*T128,*T129	Yes	T4,T128,T129	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T78,T80,T389	Yes	T78,T79,T80	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T4,*T128,*T129	Yes	T4,T128,T129	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	INPUT
tl_edn1_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T128,T8	Yes	T4,T128,T129	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T4,T128,T8	Yes	T4,T128,T129	INPUT
tl_edn1_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T4,*T128,*T129	Yes	T4,T128,T129	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T4,T128,T129	Yes	T4,T128,T129	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T80,T82	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T78,T80,T82	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_otbn_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T52,*T81,*T203	Yes	T52,T81,T203	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	INPUT
tl_otbn_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	INPUT
tl_otbn_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T52,*T81,*T203	Yes	T52,T81,T203	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T4,*T47,*T128	Yes	T4,T47,T128	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T4,T47,T128	Yes	T4,T47,T128	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T47,T154,T48	Yes	T47,T154,T48	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T47,T154,T48	Yes	T47,T154,T48	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T47,T154,T48	Yes	T47,T154,T48	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T154,T177,T110	Yes	T154,T177,T110	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T47,T154,T48	Yes	T47,T154,T48	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T47,T154,T48	Yes	T47,T154,T48	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T47,T154,T48	Yes	T47,T154,T48	INPUT
tl_keymgr_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T154,T177,T110	Yes	T154,T177,T110	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T47,T154,T48	Yes	T47,T154,T48	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T47,T154,T48	Yes	T47,T154,T48	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T47,*T154,*T48	Yes	T47,T154,T48	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T47,T154,T48	Yes	T47,T154,T48	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T50,*T52,*T58	Yes	T50,T52,T58	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T50,T52,T58	Yes	T50,T52,T58	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T50,*T52,*T58	Yes	T50,T52,T58	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T80,T210	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T47,T48,T186	Yes	T47,T48,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T47,T48,T186	Yes	T47,T48,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T47,T48,T186	Yes	T47,T48,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T47,T48,T186	Yes	T47,T48,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T47,T48,T186	Yes	T47,T48,T186	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T257,*T78,*T79	Yes	T257,T78,T79	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T47,T48,T186	Yes	T47,T48,T186	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T47,T48,T186	Yes	T47,T48,T186	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T78,T80,T82	Yes	T78,T80,T389	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T186,T187,T299	Yes	T186,T187,T299	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T186,T44,T45	Yes	T47,T48,T186	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T186,T44,T45	Yes	T47,T48,T186	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T257,T78,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T186,*T182,*T183	Yes	T186,T182,T183	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T47,T48,T186	Yes	T47,T48,T186	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T5	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range