Unified Coverage Report :: Module :: prim_edn_req

Module : prim_edn_req

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if	96.15	100.00	84.62			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.08	100.00	86.44			94.87	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_packer_fifo	68.93	100.00	90.00			85.71	0.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_edn_req

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
ALWAYS	143	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	163	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
139	1	1
143	1	1
144	1	1
146	1	1
149	1	1
163		unreachable
164		unreachable
165		unreachable
166		unreachable
167		unreachable
168		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_edn_req

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T128,T260,T261

---

Branch Coverage for Module : prim_edn_req

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	139	3	3	100.00
IF	143	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((req_i && ack_o)) ? 
-2-:	139	(word_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_edn_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOutputDiffFromPrev_A	533052859	102776298	0	0
DataOutputValid_A	533703584	4350	0	0

DataOutputDiffFromPrev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533052859	102776298	0	0
T44	0	721667	0	0
T45	0	176705	0	0
T47	133715	104072	0	0
T48	0	101315	0	0
T68	140799	0	0	0
T118	0	593669	0	0
T128	522639	395719	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T185	92279	0	0	0
T213	332707	0	0	0
T255	271682	0	0	0
T260	0	313459	0	0
T261	0	96254	0	0
T357	264148	0	0	0
T369	0	209525	0	0
T370	0	104054	0	0

DataOutputValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	4350	0	0
T1	69381	1	0	0
T2	226067	4	0	0
T3	191090	2	0	0
T4	390623	2	0	0
T5	238308	4	0	0
T6	196142	2	0	0
T15	227328	1	0	0
T90	81718	1	0	0
T91	268469	2	0	0
T92	241541	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
ALWAYS	143	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	163	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
139	1	1
143	1	1
144	1	1
146	1	1
149	1	1
163		unreachable
164		unreachable
165		unreachable
166		unreachable
167		unreachable
168		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T128,T260,T261

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	139	3	3	100.00
IF	143	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((req_i && ack_o)) ? 
-2-:	139	(word_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOutputDiffFromPrev_A	533052859	102776298	0	0
DataOutputValid_A	533703584	4350	0	0

DataOutputDiffFromPrev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533052859	102776298	0	0
T44	0	721667	0	0
T45	0	176705	0	0
T47	133715	104072	0	0
T48	0	101315	0	0
T68	140799	0	0	0
T118	0	593669	0	0
T128	522639	395719	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T185	92279	0	0	0
T213	332707	0	0	0
T255	271682	0	0	0
T260	0	313459	0	0
T261	0	96254	0	0
T357	264148	0	0	0
T369	0	209525	0	0
T370	0	104054	0	0

DataOutputValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	4350	0	0
T1	69381	1	0	0
T2	226067	4	0	0
T3	191090	2	0	0
T4	390623	2	0	0
T5	238308	4	0	0
T6	196142	2	0	0
T15	227328	1	0	0
T90	81718	1	0	0
T91	268469	2	0	0
T92	241541	1	0	0