Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T185,T50,T52
0	1	Covered	T185,T296,T297
1	0	Covered	T52

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T52,T296
1	Covered	T185,T50,T52

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T52,T296
1	Covered	T185,T50,T52

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T185,T296,T297
1	1	Covered	T185,T52,T296

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T50,T52
1	0	Covered	T185,T52,T296
1	1	Covered	T185,T296,T297

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T185,T52,T296

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T50,T52
0	Covered	T185,T52,T296

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T50,T52
0	Covered	T185,T52,T296

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1067407168	1049262424	0	0
CheckNGreaterZero_A	2054	2054	0	0
GntImpliesReady_A	1067407168	8388	0	0
GntImpliesValid_A	1067407168	8388	0	0
GrantKnown_A	1067407168	1049262424	0	0
IdxKnown_A	1067407168	1049262424	0	0
IndexIsCorrect_A	1067407168	8388	0	0
NoReadyValidNoGrant_A	1067407168	0	0	0
Priority_A	1067407168	8388	0	0
ReadyAndValidImplyGrant_A	1067407168	8388	0	0
ReqAndReadyImplyGrant_A	1067407168	8388	0	0
ReqImpliesValid_A	1067407168	8388	0	0
ValidKnown_A	1067407168	1049262424	0	0
gen_data_port_assertion.DataFlow_A	1067407168	8388	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	1049262424	0	0
T1	138762	138646	0	0
T2	452134	451908	0	0
T3	382180	381970	0	0
T4	781246	781122	0	0
T5	476616	476398	0	0
T6	392284	391934	0	0
T15	454656	454554	0	0
T90	163436	163312	0	0
T91	536938	536814	0	0
T92	483082	482972	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2054	2054	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T15	2	2	0	0
T90	2	2	0	0
T91	2	2	0	0
T92	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	8388	0	0
T68	281598	0	0	0
T69	468842	0	0	0
T128	1045278	0	0	0
T129	165872	0	0	0
T149	1315672	0	0	0
T154	1019292	0	0	0
T155	163206	0	0	0
T185	184558	2796	0	0
T213	665414	0	0	0
T296	0	2795	0	0
T297	0	2797	0	0
T298	268306	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	8388	0	0
T68	281598	0	0	0
T69	468842	0	0	0
T128	1045278	0	0	0
T129	165872	0	0	0
T149	1315672	0	0	0
T154	1019292	0	0	0
T155	163206	0	0	0
T185	184558	2796	0	0
T213	665414	0	0	0
T296	0	2795	0	0
T297	0	2797	0	0
T298	268306	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	1049262424	0	0
T1	138762	138646	0	0
T2	452134	451908	0	0
T3	382180	381970	0	0
T4	781246	781122	0	0
T5	476616	476398	0	0
T6	392284	391934	0	0
T15	454656	454554	0	0
T90	163436	163312	0	0
T91	536938	536814	0	0
T92	483082	482972	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	1049262424	0	0
T1	138762	138646	0	0
T2	452134	451908	0	0
T3	382180	381970	0	0
T4	781246	781122	0	0
T5	476616	476398	0	0
T6	392284	391934	0	0
T15	454656	454554	0	0
T90	163436	163312	0	0
T91	536938	536814	0	0
T92	483082	482972	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	8388	0	0
T68	281598	0	0	0
T69	468842	0	0	0
T128	1045278	0	0	0
T129	165872	0	0	0
T149	1315672	0	0	0
T154	1019292	0	0	0
T155	163206	0	0	0
T185	184558	2796	0	0
T213	665414	0	0	0
T296	0	2795	0	0
T297	0	2797	0	0
T298	268306	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	8388	0	0
T68	281598	0	0	0
T69	468842	0	0	0
T128	1045278	0	0	0
T129	165872	0	0	0
T149	1315672	0	0	0
T154	1019292	0	0	0
T155	163206	0	0	0
T185	184558	2796	0	0
T213	665414	0	0	0
T296	0	2795	0	0
T297	0	2797	0	0
T298	268306	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	8388	0	0
T68	281598	0	0	0
T69	468842	0	0	0
T128	1045278	0	0	0
T129	165872	0	0	0
T149	1315672	0	0	0
T154	1019292	0	0	0
T155	163206	0	0	0
T185	184558	2796	0	0
T213	665414	0	0	0
T296	0	2795	0	0
T297	0	2797	0	0
T298	268306	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	8388	0	0
T68	281598	0	0	0
T69	468842	0	0	0
T128	1045278	0	0	0
T129	165872	0	0	0
T149	1315672	0	0	0
T154	1019292	0	0	0
T155	163206	0	0	0
T185	184558	2796	0	0
T213	665414	0	0	0
T296	0	2795	0	0
T297	0	2797	0	0
T298	268306	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	8388	0	0
T68	281598	0	0	0
T69	468842	0	0	0
T128	1045278	0	0	0
T129	165872	0	0	0
T149	1315672	0	0	0
T154	1019292	0	0	0
T155	163206	0	0	0
T185	184558	2796	0	0
T213	665414	0	0	0
T296	0	2795	0	0
T297	0	2797	0	0
T298	268306	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	1049262424	0	0
T1	138762	138646	0	0
T2	452134	451908	0	0
T3	382180	381970	0	0
T4	781246	781122	0	0
T5	476616	476398	0	0
T6	392284	391934	0	0
T15	454656	454554	0	0
T90	163436	163312	0	0
T91	536938	536814	0	0
T92	483082	482972	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067407168	8388	0	0
T68	281598	0	0	0
T69	468842	0	0	0
T128	1045278	0	0	0
T129	165872	0	0	0
T149	1315672	0	0	0
T154	1019292	0	0	0
T155	163206	0	0	0
T185	184558	2796	0	0
T213	665414	0	0	0
T296	0	2795	0	0
T297	0	2797	0	0
T298	268306	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T185,T52,T58
0	1	Covered	T185,T296,T297
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T296,T297
1	Covered	T185,T52,T58

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T296,T297
1	Covered	T185,T52,T58

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T185,T296,T297
1	1	Covered	T185,T296,T297

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T52,T58
1	0	Covered	T185,T296,T297
1	1	Covered	T185,T296,T297

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T185,T296,T297

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T52,T58
0	Covered	T185,T296,T297

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T52,T58
0	Covered	T185,T296,T297

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	533703584	524631212	0	0
CheckNGreaterZero_A	1027	1027	0	0
GntImpliesReady_A	533703584	5199	0	0
GntImpliesValid_A	533703584	5199	0	0
GrantKnown_A	533703584	524631212	0	0
IdxKnown_A	533703584	524631212	0	0
IndexIsCorrect_A	533703584	5199	0	0
NoReadyValidNoGrant_A	533703584	0	0	0
Priority_A	533703584	5199	0	0
ReadyAndValidImplyGrant_A	533703584	5199	0	0
ReqAndReadyImplyGrant_A	533703584	5199	0	0
ReqImpliesValid_A	533703584	5199	0	0
ValidKnown_A	533703584	524631212	0	0
gen_data_port_assertion.DataFlow_A	533703584	5199	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	524631212	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	5199	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1734	0	0
T213	332707	0	0	0
T296	0	1732	0	0
T297	0	1733	0	0
T298	134153	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	5199	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1734	0	0
T213	332707	0	0	0
T296	0	1732	0	0
T297	0	1733	0	0
T298	134153	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	524631212	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	524631212	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	5199	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1734	0	0
T213	332707	0	0	0
T296	0	1732	0	0
T297	0	1733	0	0
T298	134153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	5199	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1734	0	0
T213	332707	0	0	0
T296	0	1732	0	0
T297	0	1733	0	0
T298	134153	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	5199	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1734	0	0
T213	332707	0	0	0
T296	0	1732	0	0
T297	0	1733	0	0
T298	134153	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	5199	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1734	0	0
T213	332707	0	0	0
T296	0	1732	0	0
T297	0	1733	0	0
T298	134153	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	5199	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1734	0	0
T213	332707	0	0	0
T296	0	1732	0	0
T297	0	1733	0	0
T298	134153	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	524631212	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	5199	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1734	0	0
T213	332707	0	0	0
T296	0	1732	0	0
T297	0	1733	0	0
T298	134153	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T185,T50,T52
0	1	Covered	T185,T296,T297
1	0	Covered	T52

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T52,T296
1	Covered	T185,T50,T52

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T185,T52,T296
1	Covered	T185,T50,T52

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T185,T296,T297
1	1	Covered	T185,T52,T296

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T50,T52
1	0	Covered	T185,T52,T296
1	1	Covered	T185,T296,T297

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T185,T52,T296

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T50,T52
0	Covered	T185,T52,T296

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T185,T50,T52
0	Covered	T185,T52,T296

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	533703584	524631212	0	0
CheckNGreaterZero_A	1027	1027	0	0
GntImpliesReady_A	533703584	3189	0	0
GntImpliesValid_A	533703584	3189	0	0
GrantKnown_A	533703584	524631212	0	0
IdxKnown_A	533703584	524631212	0	0
IndexIsCorrect_A	533703584	3189	0	0
NoReadyValidNoGrant_A	533703584	0	0	0
Priority_A	533703584	3189	0	0
ReadyAndValidImplyGrant_A	533703584	3189	0	0
ReqAndReadyImplyGrant_A	533703584	3189	0	0
ReqImpliesValid_A	533703584	3189	0	0
ValidKnown_A	533703584	524631212	0	0
gen_data_port_assertion.DataFlow_A	533703584	3189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	524631212	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	3189	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1062	0	0
T213	332707	0	0	0
T296	0	1063	0	0
T297	0	1064	0	0
T298	134153	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	3189	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1062	0	0
T213	332707	0	0	0
T296	0	1063	0	0
T297	0	1064	0	0
T298	134153	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	524631212	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	524631212	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	3189	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1062	0	0
T213	332707	0	0	0
T296	0	1063	0	0
T297	0	1064	0	0
T298	134153	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	3189	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1062	0	0
T213	332707	0	0	0
T296	0	1063	0	0
T297	0	1064	0	0
T298	134153	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	3189	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1062	0	0
T213	332707	0	0	0
T296	0	1063	0	0
T297	0	1064	0	0
T298	134153	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	3189	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1062	0	0
T213	332707	0	0	0
T296	0	1063	0	0
T297	0	1064	0	0
T298	134153	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	3189	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1062	0	0
T213	332707	0	0	0
T296	0	1063	0	0
T297	0	1064	0	0
T298	134153	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	524631212	0	0
T1	69381	69323	0	0
T2	226067	225954	0	0
T3	191090	190985	0	0
T4	390623	390561	0	0
T5	238308	238199	0	0
T6	196142	195967	0	0
T15	227328	227277	0	0
T90	81718	81656	0	0
T91	268469	268407	0	0
T92	241541	241486	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533703584	3189	0	0
T68	140799	0	0	0
T69	234421	0	0	0
T128	522639	0	0	0
T129	82936	0	0	0
T149	657836	0	0	0
T154	509646	0	0	0
T155	81603	0	0	0
T185	92279	1062	0	0
T213	332707	0	0	0
T296	0	1063	0	0
T297	0	1064	0	0
T298	134153	0	0	0