Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1027	1027	0	0
OutputsKnown_A	133998423	133298586	0	0
gen_no_flops.OutputDelay_A	133998423	133298586	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133998423	133298586	0	0
T1	17388	17019	0	0
T2	55615	54996	0	0
T3	47625	47314	0	0
T4	94454	94121	0	0
T5	58406	57936	0	0
T6	50710	49537	0	0
T15	55440	54931	0	0
T90	20442	19979	0	0
T91	65439	64802	0	0
T92	58680	58341	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133998423	133298586	0	0
T1	17388	17019	0	0
T2	55615	54996	0	0
T3	47625	47314	0	0
T4	94454	94121	0	0
T5	58406	57936	0	0
T6	50710	49537	0	0
T15	55440	54931	0	0
T90	20442	19979	0	0
T91	65439	64802	0	0
T92	58680	58341	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1027	1027	0	0
OutputsKnown_A	133998423	133298586	0	0
gen_no_flops.OutputDelay_A	133998423	133298586	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0
T92	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133998423	133298586	0	0
T1	17388	17019	0	0
T2	55615	54996	0	0
T3	47625	47314	0	0
T4	94454	94121	0	0
T5	58406	57936	0	0
T6	50710	49537	0	0
T15	55440	54931	0	0
T90	20442	19979	0	0
T91	65439	64802	0	0
T92	58680	58341	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133998423	133298586	0	0
T1	17388	17019	0	0
T2	55615	54996	0	0
T3	47625	47314	0	0
T4	94454	94121	0	0
T5	58406	57936	0	0
T6	50710	49537	0	0
T15	55440	54931	0	0
T90	20442	19979	0	0
T91	65439	64802	0	0
T92	58680	58341	0	0