Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3695952	1			T72	2573		T73	1062		T74	734
values[2]	736095	1			T73	297		T74	217		T249	466
values[3]	95358	1			T74	1		T249	3		T250	6
values[4]	50768	1			T715	1		T467	23		T714	3
values[5]	34845	1			T715	2		T467	7		T714	3
values[6]	26687	1			T715	1		T714	3		T441	185
values[7]	21770	1			T715	2		T714	3		T441	142
values[8]	18412	1			T715	1		T714	3		T441	91
values[9]	16640	1			T715	1		T714	3		T441	79
values[10]	15315	1			T715	2		T714	3		T441	61
values[11]	14258	1			T715	5		T714	3		T441	54
values[12]	13287	1			T715	4		T714	3		T441	52
values[13]	12748	1			T715	4		T714	3		T441	26
values[14]	12140	1			T715	5		T714	3		T441	28
values[15]	11523	1			T715	5		T714	3		T441	19
values[16]	11282	1			T715	3		T714	3		T441	19
values[17]	11130	1			T715	2		T714	3		T441	15
values[18]	10950	1			T715	2		T714	3		T441	15
values[19]	10579	1			T715	3		T714	3		T441	11
values[20]	10468	1			T715	3		T714	3		T441	14
values[21]	10132	1			T715	2		T714	3		T441	17
values[22]	9804	1			T715	2		T714	3		T441	25
values[23]	9299	1			T715	8		T714	3		T441	22
values[24]	8869	1			T715	1		T714	3		T441	16
values[25]	8682	1			T715	1		T714	3		T441	15
values[26]	8294	1			T715	1		T714	3		T441	11
values[27]	8212	1			T715	1		T714	3		T441	8
values[28]	7623	1			T715	1		T714	3		T441	8
values[29]	7099	1			T715	1		T714	3		T441	14
values[30]	6586	1			T715	1		T714	3		T441	13
values[31]	6094	1			T715	2		T714	3		T441	18
values[32]	5742	1			T715	1		T714	3		T441	14
values[33]	5256	1			T715	2		T714	3		T441	8
values[34]	4881	1			T715	1		T714	3		T441	13
values[35]	4538	1			T715	1		T714	3		T441	14
values[36]	4107	1			T715	1		T714	3		T441	12
values[37]	3839	1			T715	2		T714	3		T441	14
values[38]	3866	1			T715	2		T714	3		T441	9
values[39]	3679	1			T715	2		T714	3		T441	6
values[40]	3597	1			T715	7		T714	3		T441	13
values[41]	3508	1			T715	2		T714	3		T441	7
values[42]	3386	1			T715	1		T714	3		T441	7
values[43]	3275	1			T715	2		T714	4		T441	10
values[44]	3080	1			T715	1		T714	3		T441	12
values[45]	3081	1			T715	3		T714	3		T441	11
values[46]	2953	1			T715	2		T714	3		T441	7
values[47]	2992	1			T715	3		T714	3		T441	8
values[48]	2942	1			T715	3		T714	3		T441	7
values[49]	2856	1			T715	4		T714	3		T441	9
values[50]	2808	1			T715	5		T714	3		T441	8
values[51]	2701	1			T715	2		T714	3		T441	11
values[52]	2758	1			T715	2		T714	3		T441	14
values[53]	2649	1			T715	4		T714	3		T441	12
values[54]	2662	1			T715	2		T714	3		T441	15
values[55]	2581	1			T715	3		T714	3		T441	19
values[56]	2503	1			T715	4		T714	3		T441	21
values[57]	2382	1			T715	1		T714	3		T441	26
values[58]	2418	1			T715	2		T714	3		T441	15
values[59]	2407	1			T715	1		T714	3		T441	12
values[60]	2399	1			T715	2		T714	3		T441	11
values[61]	2633	1			T715	1		T714	3		T441	24
values[62]	3785	1			T715	2		T714	3		T441	56
values[63]	10286	1			T715	4		T714	3		T441	110
values[64]	230655	1			T715	73		T714	580		T441	289

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4711288	1			T72	2531		T73	1277		T74	719
values[2]	810959	1			T73	341		T74	201		T249	502
values[3]	82382	1			T73	8		T74	1		T249	76
values[4]	14423	1			T73	1		T249	1		T250	1
values[5]	5350	1			T467	10		T714	3		T440	10
values[6]	3232	1			T467	6		T714	2		T440	4
values[7]	2559	1			T714	2		T440	3		T441	50
values[8]	2077	1			T714	1		T440	1		T441	35
values[9]	1777	1			T714	1		T441	28		T655	5
values[10]	1611	1			T714	1		T441	28		T655	6
values[11]	1427	1			T714	1		T441	17		T655	2
values[12]	1409	1			T714	1		T441	9		T655	7
values[13]	1283	1			T714	1		T441	8		T655	7
values[14]	1200	1			T714	1		T441	9		T655	5
values[15]	1209	1			T714	1		T441	8		T655	3
values[16]	1126	1			T714	1		T441	13		T655	4
values[17]	1013	1			T714	1		T441	5		T655	3
values[18]	933	1			T714	1		T441	9		T655	2
values[19]	919	1			T714	1		T441	4		T655	2
values[20]	899	1			T714	1		T441	2		T655	2
values[21]	793	1			T714	1		T441	5		T655	3
values[22]	765	1			T714	1		T441	5		T655	3
values[23]	724	1			T714	1		T441	21		T655	2
values[24]	677	1			T714	1		T441	9		T655	2
values[25]	707	1			T714	1		T441	11		T655	4
values[26]	632	1			T714	1		T441	5		T655	2
values[27]	627	1			T714	1		T441	4		T655	4
values[28]	589	1			T714	1		T441	4		T655	5
values[29]	595	1			T714	2		T441	1		T655	4
values[30]	606	1			T714	1		T441	4		T655	4
values[31]	565	1			T714	1		T441	3		T655	6
values[32]	533	1			T714	1		T441	5		T655	5
values[33]	467	1			T714	1		T441	1		T655	2
values[34]	482	1			T714	2		T441	2		T655	3
values[35]	484	1			T714	1		T441	2		T655	4
values[36]	453	1			T714	1		T441	4		T655	7
values[37]	454	1			T714	1		T441	8		T655	8
values[38]	396	1			T714	1		T441	3		T655	4
values[39]	450	1			T714	1		T441	4		T655	3
values[40]	461	1			T714	1		T441	1		T655	4
values[41]	454	1			T714	1		T441	1		T655	3
values[42]	440	1			T714	1		T441	1		T655	5
values[43]	436	1			T714	1		T441	1		T655	5
values[44]	391	1			T714	1		T441	1		T655	4
values[45]	424	1			T714	1		T441	1		T655	4
values[46]	431	1			T714	1		T441	1		T655	5
values[47]	423	1			T714	1		T441	1		T655	6
values[48]	405	1			T714	1		T441	1		T655	3
values[49]	395	1			T714	1		T441	1		T655	3
values[50]	373	1			T714	1		T441	1		T655	5
values[51]	388	1			T714	1		T441	1		T655	4
values[52]	376	1			T714	1		T441	1		T655	4
values[53]	366	1			T714	1		T441	4		T655	2
values[54]	380	1			T714	1		T441	2		T655	3
values[55]	391	1			T714	1		T441	1		T655	4
values[56]	364	1			T714	1		T441	1		T655	4
values[57]	370	1			T714	1		T441	2		T655	4
values[58]	345	1			T714	1		T441	1		T655	3
values[59]	363	1			T714	1		T441	1		T655	3
values[60]	340	1			T714	1		T441	2		T655	5
values[61]	362	1			T714	1		T441	3		T655	6
values[62]	655	1			T714	1		T441	8		T655	11
values[63]	2422	1			T714	1		T441	33		T655	48
values[64]	26373	1			T714	226		T441	65		T655	136

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	538834	1			T72	2435		T73	10		T74	6
values[2]	2660801	1			T73	1190		T74	719		T249	881
values[3]	1177130	1			T73	322		T74	203		T249	1694
values[4]	140440	1			T74	1		T249	42		T250	1
values[5]	70649	1			T536	4		T715	2		T467	107
values[6]	45623	1			T536	1		T715	6		T467	51
values[7]	33320	1			T715	2		T467	44		T714	3
values[8]	26478	1			T715	3		T467	47		T714	3
values[9]	22683	1			T715	8		T467	26		T714	3
values[10]	20066	1			T715	3		T467	18		T714	3
values[11]	18432	1			T715	3		T467	28		T714	3
values[12]	17147	1			T715	3		T467	22		T714	3
values[13]	16025	1			T715	5		T467	9		T714	3
values[14]	15021	1			T715	11		T467	9		T714	3
values[15]	14617	1			T715	2		T467	2		T714	3
values[16]	14152	1			T715	2		T467	3		T714	3
values[17]	13235	1			T715	1		T467	1		T714	3
values[18]	12663	1			T715	4		T467	2		T714	3
values[19]	11905	1			T715	5		T467	1		T714	3
values[20]	11454	1			T715	2		T467	2		T714	3
values[21]	11157	1			T715	1		T467	4		T714	4
values[22]	10958	1			T715	3		T467	1		T714	3
values[23]	10580	1			T715	2		T467	2		T714	3
values[24]	10094	1			T715	2		T467	1		T714	3
values[25]	9738	1			T715	1		T714	3		T441	29
values[26]	9296	1			T715	1		T714	3		T441	20
values[27]	8747	1			T715	1		T714	3		T441	18
values[28]	8340	1			T715	4		T714	3		T441	23
values[29]	7920	1			T715	6		T714	3		T441	19
values[30]	7322	1			T715	4		T714	3		T441	9
values[31]	6710	1			T715	4		T714	3		T441	13
values[32]	6167	1			T715	2		T714	3		T441	9
values[33]	5610	1			T715	1		T714	3		T441	18
values[34]	5273	1			T715	1		T714	3		T441	11
values[35]	5181	1			T715	4		T714	3		T441	18
values[36]	4765	1			T715	7		T714	3		T441	18
values[37]	4415	1			T715	2		T714	3		T441	12
values[38]	4123	1			T715	1		T714	3		T441	16
values[39]	3948	1			T715	2		T714	3		T441	18
values[40]	3757	1			T715	3		T714	3		T441	25
values[41]	3683	1			T715	1		T714	4		T441	11
values[42]	3657	1			T715	3		T714	3		T441	18
values[43]	3513	1			T715	3		T714	3		T441	15
values[44]	3468	1			T715	1		T714	3		T441	19
values[45]	3277	1			T715	1		T714	3		T441	19
values[46]	3317	1			T715	3		T714	3		T441	22
values[47]	3212	1			T715	2		T714	3		T441	19
values[48]	3261	1			T715	1		T714	3		T441	19
values[49]	3227	1			T715	3		T714	3		T441	9
values[50]	3194	1			T715	4		T714	3		T441	9
values[51]	3121	1			T715	5		T714	3		T441	14
values[52]	3051	1			T715	2		T714	3		T441	15
values[53]	2934	1			T715	4		T714	3		T441	11
values[54]	3055	1			T715	10		T714	3		T441	31
values[55]	2970	1			T715	6		T714	3		T441	26
values[56]	2868	1			T715	12		T714	3		T441	19
values[57]	2892	1			T715	8		T714	3		T441	33
values[58]	2756	1			T715	6		T714	3		T441	25
values[59]	2663	1			T715	4		T714	3		T441	15
values[60]	2593	1			T715	8		T714	3		T441	13
values[61]	2746	1			T715	1		T714	3		T441	10
values[62]	3565	1			T715	1		T714	3		T441	27
values[63]	9014	1			T715	6		T714	4		T441	132
values[64]	220701	1			T715	75		T714	472		T441	307