Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2197798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37658579

1

T1

11173

T2

58586

T3

10901

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28073934	1			T1	4065		T2	36057		T3	5116
values[0x0]	10250698	1			T1	7108		T2	22529		T3	5785
values[0x1]	1531745	1			T1	305		T3	414		T4	887

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	769218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39087159

1

T1

11478

T2

58586

T3

11315

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18603481	1			T1	5739		T2	29293		T3	5658
valid_sources[0x01]	18603320	1			T1	5739		T2	29293		T3	5657
valid_sources[0x02]	42387	1			T51	4		T199	1		T637	1
valid_sources[0x03]	43082	1			T76	1		T378	128		T141	97
valid_sources[0x04]	43331	1			T199	2		T637	3		T378	102
valid_sources[0x05]	42356	1			T51	1		T199	1		T637	1
valid_sources[0x06]	42561	1			T76	1		T51	2		T77	1
valid_sources[0x07]	50396	1			T76	1		T199	1		T637	3
valid_sources[0x08]	42870	1			T198	2		T637	3		T378	124
valid_sources[0x09]	42925	1			T76	1		T51	1		T77	2
valid_sources[0x0a]	41968	1			T51	4		T199	2		T637	4
valid_sources[0x0b]	42283	1			T637	1		T378	108		T141	130
valid_sources[0x0c]	43084	1			T76	2		T198	1		T199	4
valid_sources[0x0d]	43489	1			T198	2		T637	4		T378	126
valid_sources[0x0e]	43111	1			T76	1		T198	4		T199	2
valid_sources[0x0f]	42056	1			T51	1		T637	2		T378	127
valid_sources[0x10]	41907	1			T51	2		T77	4		T59	7
valid_sources[0x11]	45066	1			T51	2		T77	1		T199	1
valid_sources[0x12]	42288	1			T76	2		T51	1		T637	5
valid_sources[0x13]	42469	1			T59	18		T378	108		T141	111
valid_sources[0x14]	42325	1			T637	1		T378	102		T141	105
valid_sources[0x15]	42829	1			T76	1		T199	1		T637	6
valid_sources[0x16]	42798	1			T637	6		T378	153		T141	131
valid_sources[0x17]	42472	1			T51	2		T378	142		T141	124
valid_sources[0x18]	45754	1			T76	3		T51	1		T77	2
valid_sources[0x19]	42772	1			T51	1		T198	9		T637	10
valid_sources[0x1a]	42574	1			T77	1		T378	134		T141	144
valid_sources[0x1b]	42467	1			T51	1		T199	1		T637	10
valid_sources[0x1c]	41687	1			T76	3		T51	1		T198	2
valid_sources[0x1d]	42064	1			T51	1		T198	7		T199	1
valid_sources[0x1e]	42606	1			T199	1		T637	3		T378	148
valid_sources[0x1f]	42007	1			T199	1		T637	2		T378	151
valid_sources[0x20]	42896	1			T637	6		T378	165		T141	120

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27204164

1

T1

4065

T2

36057

T3

5116

values[0x0]

all_enables

biggest_size

10197389

1

T1

7108

T2

22529

T3

5785

values[0x1]

all_enables

biggest_size

257026

1

T76

24

T51

14

T77

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2855925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

452014

1

T72

349

T73

11

T74

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1119767	1			T72	831		T73	20		T74	19
values[0x0]	1069215	1			T72	864		T73	5		T74	3
values[0x1]	1118957	1			T72	878		T73	33		T74	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2212272	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1095667

1

T72

841

T73

33

T74

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50116	1			T72	28		T73	1		T249	25
valid_sources[0x01]	51203	1			T72	63		T74	1		T249	42
valid_sources[0x02]	51339	1			T72	50		T73	5		T74	1
valid_sources[0x03]	52611	1			T72	64		T73	2		T249	35
valid_sources[0x04]	51734	1			T72	80		T74	1		T249	47
valid_sources[0x05]	51769	1			T72	13		T249	29		T250	2
valid_sources[0x06]	51372	1			T72	34		T74	2		T249	58
valid_sources[0x07]	51935	1			T72	19		T74	1		T249	40
valid_sources[0x08]	51838	1			T72	39		T73	2		T74	1
valid_sources[0x09]	51665	1			T72	32		T73	1		T74	1
valid_sources[0x0a]	52484	1			T72	31		T73	1		T74	1
valid_sources[0x0b]	50989	1			T72	81		T249	20		T250	1
valid_sources[0x0c]	52360	1			T72	48		T73	1		T249	42
valid_sources[0x0d]	52932	1			T72	49		T249	22		T250	8
valid_sources[0x0e]	51731	1			T72	14		T73	1		T249	25
valid_sources[0x0f]	51739	1			T72	47		T73	2		T249	29
valid_sources[0x10]	52165	1			T72	101		T249	50		T250	1
valid_sources[0x11]	50973	1			T72	39		T249	18		T251	1
valid_sources[0x12]	52369	1			T72	69		T74	1		T249	33
valid_sources[0x13]	50688	1			T72	64		T73	1		T249	30
valid_sources[0x14]	51976	1			T72	41		T73	2		T74	2
valid_sources[0x15]	51915	1			T72	16		T249	32		T250	3
valid_sources[0x16]	51930	1			T72	69		T74	1		T249	25
valid_sources[0x17]	51374	1			T72	75		T73	1		T74	1
valid_sources[0x18]	50968	1			T72	49		T249	32		T536	10
valid_sources[0x19]	51162	1			T72	25		T249	54		T250	5
valid_sources[0x1a]	50763	1			T72	16		T73	1		T249	24
valid_sources[0x1b]	51646	1			T72	49		T73	3		T74	3
valid_sources[0x1c]	51136	1			T73	1		T249	29		T251	2
valid_sources[0x1d]	52285	1			T72	65		T249	32		T250	7
valid_sources[0x1e]	53260	1			T72	8		T73	1		T74	2
valid_sources[0x1f]	51803	1			T72	15		T73	2		T249	20
valid_sources[0x20]	50932	1			T72	43		T73	1		T74	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47498

1

T72

38

T73

6

T249

24

values[0x0]

all_enables

biggest_size

357090

1

T72

280

T73

2

T74

2

values[0x1]

all_enables

biggest_size

47426

1

T72

31

T73

3

T74

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3041874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

496341

1

T72

362

T73

7

T74

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1211393	1			T72	802		T73	33		T74	22
values[0x0]	1116458	1			T72	832		T73	6		T74	2
values[0x1]	1210364	1			T72	897		T73	32		T74	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2335314	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1202901

1

T72

832

T73

31

T74

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54684	1			T72	25		T249	30		T251	2
valid_sources[0x01]	54668	1			T72	73		T249	25		T251	1
valid_sources[0x02]	55120	1			T72	54		T73	4		T74	1
valid_sources[0x03]	54928	1			T72	44		T73	1		T249	33
valid_sources[0x04]	55302	1			T72	74		T73	1		T74	1
valid_sources[0x05]	55519	1			T72	10		T73	2		T249	39
valid_sources[0x06]	54183	1			T72	32		T73	2		T249	40
valid_sources[0x07]	56241	1			T72	37		T73	2		T74	1
valid_sources[0x08]	54813	1			T72	66		T249	47		T250	9
valid_sources[0x09]	54948	1			T72	34		T73	2		T74	1
valid_sources[0x0a]	55838	1			T72	25		T73	2		T74	2
valid_sources[0x0b]	54439	1			T72	86		T73	3		T74	1
valid_sources[0x0c]	55147	1			T72	31		T249	28		T250	1
valid_sources[0x0d]	54748	1			T72	62		T73	1		T74	1
valid_sources[0x0e]	55253	1			T72	23		T73	1		T249	44
valid_sources[0x0f]	55536	1			T72	37		T249	36		T536	33
valid_sources[0x10]	54963	1			T72	115		T73	1		T249	31
valid_sources[0x11]	54577	1			T72	48		T249	33		T536	47
valid_sources[0x12]	55858	1			T72	47		T249	41		T251	1
valid_sources[0x13]	55524	1			T72	56		T249	25		T250	11
valid_sources[0x14]	55703	1			T72	51		T73	2		T74	1
valid_sources[0x15]	54870	1			T72	16		T73	1		T249	51
valid_sources[0x16]	55555	1			T72	58		T249	37		T250	1
valid_sources[0x17]	53423	1			T72	70		T73	3		T74	1
valid_sources[0x18]	56333	1			T72	43		T73	3		T74	1
valid_sources[0x19]	56475	1			T72	41		T73	3		T74	2
valid_sources[0x1a]	54824	1			T72	16		T74	3		T249	43
valid_sources[0x1b]	54641	1			T72	54		T249	26		T536	29
valid_sources[0x1c]	55192	1			T73	1		T74	1		T249	41
valid_sources[0x1d]	55243	1			T72	58		T74	1		T249	45
valid_sources[0x1e]	55912	1			T72	13		T249	36		T250	1
valid_sources[0x1f]	55134	1			T72	13		T249	31		T250	7
valid_sources[0x20]	55497	1			T72	48		T73	3		T249	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51899

1

T72

38

T73

2

T74

1

values[0x0]

all_enables

biggest_size

392720

1

T72

288

T73

5

T74

1

values[0x1]

all_enables

biggest_size

51722

1

T72

36

T249

40

T250

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2881202	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

455958

1

T72

324

T73

5

T74

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1130101	1			T72	807		T73	28		T74	14
values[0x0]	1077289	1			T72	819		T73	7		T74	1
values[0x1]	1129770	1			T72	809		T73	35		T74	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2231515	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1105645

1

T72

805

T73

20

T74

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51167	1			T72	24		T73	2		T249	37
valid_sources[0x01]	51707	1			T72	65		T73	3		T249	51
valid_sources[0x02]	52911	1			T72	58		T249	54		T250	1
valid_sources[0x03]	52003	1			T72	57		T74	1		T249	31
valid_sources[0x04]	51876	1			T72	63		T249	33		T251	1
valid_sources[0x05]	51926	1			T72	6		T73	3		T249	57
valid_sources[0x06]	51386	1			T72	32		T73	3		T249	42
valid_sources[0x07]	51756	1			T72	23		T73	1		T249	34
valid_sources[0x08]	52657	1			T72	53		T249	29		T250	1
valid_sources[0x09]	51844	1			T72	32		T73	1		T249	32
valid_sources[0x0a]	51791	1			T72	26		T73	2		T249	38
valid_sources[0x0b]	52229	1			T72	79		T73	1		T249	42
valid_sources[0x0c]	53122	1			T72	38		T73	6		T74	1
valid_sources[0x0d]	52364	1			T72	46		T73	1		T74	1
valid_sources[0x0e]	52815	1			T72	27		T73	1		T249	14
valid_sources[0x0f]	52687	1			T72	38		T73	2		T249	32
valid_sources[0x10]	52361	1			T72	86		T249	40		T250	8
valid_sources[0x11]	51394	1			T72	47		T249	51		T250	3
valid_sources[0x12]	52707	1			T72	54		T74	1		T249	38
valid_sources[0x13]	52032	1			T72	49		T73	1		T74	1
valid_sources[0x14]	51941	1			T72	37		T73	1		T74	1
valid_sources[0x15]	52367	1			T72	10		T249	46		T250	3
valid_sources[0x16]	51721	1			T72	86		T73	2		T74	2
valid_sources[0x17]	51459	1			T72	57		T249	39		T250	2
valid_sources[0x18]	51631	1			T72	28		T73	1		T249	45
valid_sources[0x19]	52476	1			T72	32		T74	1		T249	31
valid_sources[0x1a]	51910	1			T72	17		T73	3		T249	23
valid_sources[0x1b]	51956	1			T72	47		T73	2		T74	1
valid_sources[0x1c]	52423	1			T73	1		T74	1		T249	34
valid_sources[0x1d]	52214	1			T72	43		T249	59		T250	2
valid_sources[0x1e]	53212	1			T72	18		T249	34		T250	7
valid_sources[0x1f]	51451	1			T72	15		T74	1		T249	52
valid_sources[0x20]	51821	1			T72	52		T249	56		T250	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47818

1

T72

32

T73

1

T74

1

values[0x0]

all_enables

biggest_size

360170

1

T72

261

T73

2

T74

1

values[0x1]

all_enables

biggest_size

47970

1

T72

31

T73

2

T74

1