Unified Coverage Report :: Module :: ibex_top

Module : ibex_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.46			93.46

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core	95.78			95.78

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78			95.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78			95.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : ibex_top

	Total	Covered	Percent
Totals	42	32	76.19
Total Bits	826	772	93.46
Total Bits 0->1	413	387	93.70
Total Bits 1->0	413	385	93.22

Ports	42	32	76.19
Port Bits	826	772	93.46
Port Bits 0->1	413	387	93.70
Port Bits 1->0	413	385	93.22

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
instr_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
instr_addr_o[18:17]	No	No		No		OUTPUT
instr_addr_o[19]	No	No		Yes	T279,T384,T385	OUTPUT
instr_addr_o[27:20]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	*T2,*T241,*T259	Yes	T2,T75,T241	OUTPUT
instr_addr_o[31:30]	No	No		No		OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_err_i	Yes	Yes	T2,T4,T64	Yes	T2,T4,T64	INPUT
data_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_we_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_be_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_err_i	Yes	Yes	T2,T4,T64	Yes	T2,T4,T64	INPUT
irq_software_i	Yes	Yes	T51,T252,T253	Yes	T51,T252,T253	INPUT
irq_timer_i	Yes	Yes	T151,T254,T255	Yes	T151,T254,T255	INPUT
irq_external_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T4,T64,T49	Yes	T4,T64,T49	INPUT
scramble_key_valid_i	Yes	Yes	T176,T177,T179	Yes	T176,T177,T179	INPUT
scramble_key_i[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T4,T35	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T1,T2,T35	Yes	T1,T2,T3	INPUT
scramble_req_o	Yes	Yes	T176,T177,T178	Yes	T176,T177,T178	OUTPUT
debug_req_i	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T242,T243,T244	Yes	T242,T243,T244	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
alert_minor_o	No	No		No		OUTPUT
alert_major_internal_o	No	No		Yes	T386	OUTPUT
alert_major_bus_o	Yes	Yes	T1,T113,T241	Yes	T1,T113,T241	OUTPUT
core_sleep_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

	Total	Covered	Percent
Totals	38	32	84.21
Total Bits	806	772	95.78
Total Bits 0->1	403	387	96.03
Total Bits 1->0	403	385	95.53

Ports	38	32	84.21
Port Bits	806	772	95.78
Port Bits 0->1	403	387	96.03
Port Bits 1->0	403	385	95.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
instr_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
instr_addr_o[18:17]	No	No		No		OUTPUT
instr_addr_o[19]	No	No		Yes	T279,T384,T385	OUTPUT
instr_addr_o[27:20]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	*T2,*T241,*T259	Yes	T2,T75,T241	OUTPUT
instr_addr_o[31:30]	No	No		No		OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_err_i	Yes	Yes	T2,T4,T64	Yes	T2,T4,T64	INPUT
data_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_we_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_be_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_err_i	Yes	Yes	T2,T4,T64	Yes	T2,T4,T64	INPUT
irq_software_i	Yes	Yes	T51,T252,T253	Yes	T51,T252,T253	INPUT
irq_timer_i	Yes	Yes	T151,T254,T255	Yes	T151,T254,T255	INPUT
irq_external_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T4,T64,T49	Yes	T4,T64,T49	INPUT
scramble_key_valid_i	Yes	Yes	T176,T177,T179	Yes	T176,T177,T179	INPUT
scramble_key_i[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T4,T35	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T1,T2,T35	Yes	T1,T2,T3	INPUT
scramble_req_o	Yes	Yes	T176,T177,T178	Yes	T176,T177,T178	OUTPUT
debug_req_i	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T242,T243,T244	Yes	T242,T243,T244	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
alert_minor_o	No	No		No		OUTPUT
alert_major_internal_o	No	No		Yes	T386	OUTPUT
alert_major_bus_o	Yes	Yes	T1,T113,T241	Yes	T1,T113,T241	OUTPUT
core_sleep_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range