Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530118484	61280101	0	0
DepthKnown_A	530118484	530012474	0	0
RvalidKnown_A	530118484	530012474	0	0
WreadyKnown_A	530118484	530012474	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	61280101	0	0
T1	176784	20800	0	0
T2	828076	706651	0	0
T3	119013	14977	0	0
T4	227182	29680	0	0
T5	128744	17629	0	0
T6	203811	38729	0	0
T7	902738	461204	0	0
T19	171722	18986	0	0
T35	165207	12533	0	0
T83	211662	18719	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530118484	47463837	0	0
DepthKnown_A	530118484	530012474	0	0
RvalidKnown_A	530118484	530012474	0	0
WreadyKnown_A	530118484	530012474	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	47463837	0	0
T1	176784	14980	0	0
T2	828076	297636	0	0
T3	119013	11912	0	0
T4	227182	20151	0	0
T5	128744	12388	0	0
T6	203811	28803	0	0
T7	902738	234493	0	0
T19	171722	16147	0	0
T35	165207	8321	0	0
T83	211662	14513	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530118484	44171801	0	0
DepthKnown_A	530118484	530012474	0	0
RvalidKnown_A	530118484	530012474	0	0
WreadyKnown_A	530118484	530012474	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	44171801	0	0
T1	176784	11861	0	0
T2	828076	251300	0	0
T3	119013	11475	0	0
T4	227182	14323	0	0
T5	128744	6754	0	0
T6	203811	23070	0	0
T7	902738	42281	0	0
T19	171722	11083	0	0
T35	165207	6134	0	0
T83	211662	10637	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530118484	37191839	0	0
DepthKnown_A	530118484	530012474	0	0
RvalidKnown_A	530118484	530012474	0	0
WreadyKnown_A	530118484	530012474	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	37191839	0	0
T1	176784	11478	0	0
T2	828076	58586	0	0
T3	119013	11315	0	0
T4	227182	13945	0	0
T5	128744	6471	0	0
T6	203811	22532	0	0
T7	902738	39130	0	0
T19	171722	10952	0	0
T35	165207	5889	0	0
T83	211662	10392	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530118484	530012474	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	616902373	101590	0	0
DepthKnown_A	616902373	616780469	0	0
RvalidKnown_A	616902373	616780469	0	0
WreadyKnown_A	616902373	616780469	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	101590	0	0
T1	176784	106	0	0
T2	828076	2	0	0
T3	119013	68	0	0
T4	227182	151	0	0
T5	128744	26	0	0
T6	203811	15	0	0
T7	902738	98	0	0
T19	171722	13	0	0
T35	165207	30	0	0
T83	211662	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	616902373	105223	0	0
DepthKnown_A	616902373	616780469	0	0
RvalidKnown_A	616902373	616780469	0	0
WreadyKnown_A	616902373	616780469	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	105223	0	0
T1	176784	106	0	0
T2	828076	2	0	0
T3	119013	68	0	0
T4	227182	151	0	0
T5	128744	26	0	0
T6	203811	15	0	0
T7	902738	98	0	0
T19	171722	13	0	0
T35	165207	30	0	0
T83	211662	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	616902373	51692	0	0
DepthKnown_A	616902373	616780469	0	0
RvalidKnown_A	616902373	616780469	0	0
WreadyKnown_A	616902373	616780469	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	51692	0	0
T1	176784	100	0	0
T2	828076	1	0	0
T3	119013	67	0	0
T4	227182	95	0	0
T5	128744	23	0	0
T6	203811	12	0	0
T7	902738	98	0	0
T19	171722	12	0	0
T35	165207	28	0	0
T83	211662	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	616902373	51692	0	0
DepthKnown_A	616902373	616780469	0	0
RvalidKnown_A	616902373	616780469	0	0
WreadyKnown_A	616902373	616780469	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	51692	0	0
T1	176784	100	0	0
T2	828076	1	0	0
T3	119013	67	0	0
T4	227182	95	0	0
T5	128744	23	0	0
T6	203811	12	0	0
T7	902738	98	0	0
T19	171722	12	0	0
T35	165207	28	0	0
T83	211662	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	616902373	49898	0	0
DepthKnown_A	616902373	616780469	0	0
RvalidKnown_A	616902373	616780469	0	0
WreadyKnown_A	616902373	616780469	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	49898	0	0
T1	176784	6	0	0
T2	828076	1	0	0
T3	119013	1	0	0
T4	227182	56	0	0
T5	128744	3	0	0
T6	203811	3	0	0
T7	902738	0	0	0
T19	171722	1	0	0
T35	165207	2	0	0
T64	0	56	0	0
T83	211662	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	616902373	53531	0	0
DepthKnown_A	616902373	616780469	0	0
RvalidKnown_A	616902373	616780469	0	0
WreadyKnown_A	616902373	616780469	0	0
gen_passthru_fifo.paramCheckPass	2938	2938	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	53531	0	0
T1	176784	6	0	0
T2	828076	1	0	0
T3	119013	1	0	0
T4	227182	56	0	0
T5	128744	3	0	0
T6	203811	3	0	0
T7	902738	0	0	0
T19	171722	1	0	0
T35	165207	2	0	0
T64	0	56	0	0
T83	211662	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	616902373	616780469	0	0
T1	176784	176678	0	0
T2	828076	828014	0	0
T3	119013	118951	0	0
T4	227182	227076	0	0
T5	128744	128686	0	0
T6	203811	203749	0	0
T7	902738	902104	0	0
T19	171722	171671	0	0
T35	165207	165094	0	0
T83	211662	211552	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2938	2938	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T83	1	1	0	0