Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T8,T49	Yes	T2,T8,T49	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T8,T49	Yes	T2,T8,T49	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	INPUT
tl_i.a_valid	Yes	Yes	T2,T8,T49	Yes	T2,T8,T49	INPUT
tl_o.a_ready	Yes	Yes	T2,T8,T47	Yes	T2,T8,T47	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T8,T47,T97	Yes	T8,T47,T97	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T8,T47	Yes	T2,T8,T47	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T8,T47	Yes	T2,T8,T47	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T259,*T673,*T72	Yes	T259,T673,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T8,*T47	Yes	T2,T8,T47	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T8,T47	Yes	T2,T8,T47	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T5,T64,T362	Yes	T5,T64,T362	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T154,T79	Yes	T78,T154,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T154,T79	Yes	T78,T154,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T5,T64,T362	Yes	T5,T64,T362	OUTPUT
cio_rx_i	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T2,T8,T47	Yes	T2,T8,T47	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T8,T144,T97	Yes	T8,T144,T97	OUTPUT
intr_tx_empty_o	Yes	Yes	T8,T144,T97	Yes	T8,T144,T97	OUTPUT
intr_rx_watermark_o	Yes	Yes	T8,T144,T97	Yes	T8,T144,T97	OUTPUT
intr_tx_done_o	Yes	Yes	T8,T144,T97	Yes	T8,T144,T97	OUTPUT
intr_rx_overflow_o	Yes	Yes	T8,T144,T97	Yes	T8,T144,T97	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T49,T68	Yes	T2,T49,T68	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T49,T68	Yes	T2,T49,T68	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	INPUT
tl_i.a_valid	Yes	Yes	T2,T49,T68	Yes	T2,T49,T68	INPUT
tl_o.a_ready	Yes	Yes	T2,T47,T97	Yes	T2,T47,T97	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T47,T97,T48	Yes	T47,T97,T48	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T47,T97	Yes	T2,T47,T97	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T47,T97	Yes	T2,T47,T97	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T259,*T673,*T72	Yes	T259,T673,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T47,*T97	Yes	T2,T47,T97	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T47,T97	Yes	T2,T47,T97	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T5,T78,T154	Yes	T5,T78,T154	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T154,T79	Yes	T78,T154,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T154,T79	Yes	T78,T154,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T5,T78,T154	Yes	T5,T78,T154	OUTPUT
cio_rx_i	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T2,T47,T97	Yes	T2,T47,T97	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T97,T216,T318	Yes	T97,T216,T318	OUTPUT
intr_tx_empty_o	Yes	Yes	T97,T216,T318	Yes	T97,T216,T318	OUTPUT
intr_rx_watermark_o	Yes	Yes	T97,T216,T318	Yes	T97,T216,T318	OUTPUT
intr_tx_done_o	Yes	Yes	T97,T336,T216	Yes	T97,T336,T216	OUTPUT
intr_rx_overflow_o	Yes	Yes	T97,T336,T216	Yes	T97,T336,T216	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	INPUT
tl_i.a_valid	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	INPUT
tl_o.a_ready	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T99,*T102,*T337	Yes	T99,T102,T337	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
cio_rx_i	Yes	Yes	T99,T102,T337	Yes	T13,T99,T102	INPUT
cio_tx_o	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
intr_tx_empty_o	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
intr_rx_watermark_o	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
intr_tx_done_o	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
intr_rx_overflow_o	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	INPUT
tl_i.a_valid	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	INPUT
tl_o.a_ready	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T8,*T144,*T329	Yes	T8,T144,T329	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
cio_rx_i	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	INPUT
cio_tx_o	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
intr_tx_empty_o	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
intr_rx_watermark_o	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
intr_tx_done_o	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
intr_rx_overflow_o	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	INPUT
tl_i.a_valid	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	INPUT
tl_o.a_ready	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
tl_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T16,*T18,*T317	Yes	T16,T18,T317	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T64,T362,T78	Yes	T64,T362,T78	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T154,T79	Yes	T78,T154,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T154,T79	Yes	T78,T154,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T64,T362,T78	Yes	T64,T362,T78	OUTPUT
cio_rx_i	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	INPUT
cio_tx_o	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
intr_tx_empty_o	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
intr_rx_watermark_o	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
intr_tx_done_o	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
intr_rx_overflow_o	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_break_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_timeout_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T318,T319,T334	Yes	T318,T319,T334	OUTPUT

*Tests covering at least one bit in the range