Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T249,T250,T251	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T73,T74,T249	Yes	T73,T74,T249	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T2,T4,T64	Yes	T2,T4,T64	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T4,T64	Yes	T2,T4,T64	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T76,T72,T73	Yes	T76,T72,T73	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T76,T72,T73	Yes	T76,T72,T73	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T2,T4,T64	Yes	T2,T4,T64	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T2,T50,T75	Yes	T2,T50,T75	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T2,T50,T65	Yes	T2,T50,T65	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T2,T50,T75	Yes	T2,T50,T75	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T2,T50,T65	Yes	T2,T50,T65	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T50,T75	Yes	T2,T50,T75	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T2,T65,T76	Yes	T2,T65,T76	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T2,T50,T75	Yes	T2,T50,T75	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T59,T72,T73	Yes	T59,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T59,T72,T73	Yes	T59,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T59,T72,T73	Yes	T59,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T59,T72,T73	Yes	T59,T72,T73	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T59,T72,T73	Yes	T59,T72,T73	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T59,T249,T250	Yes	T59,T72,T73	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T72,T73	Yes	T59,T72,T73	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T59,T72,T73	Yes	T59,T72,T73	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T59,T72,T73	Yes	T59,T72,T73	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T59,*T72,*T73	Yes	T59,T72,T73	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T59,T72,T73	Yes	T59,T72,T73	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T2,*T75,*T259	Yes	T2,T75,T259	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T2,*T75,*T259	Yes	T2,T75,T259	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T4	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T2,T75,T259	Yes	T2,T75,T259	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T7,T50,T47	Yes	T7,T50,T47	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T7,T47,T48	Yes	T7,T47,T48	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T383,T397,T52	Yes	T383,T397,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T383,T397,T52	Yes	T383,T397,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T383,T397,T52	Yes	T383,T397,T52	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T59,T72,*T73	Yes	T59,T72,T73	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T383,T397,T52	Yes	T383,T397,T52	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T383,T397,T52	Yes	T383,T397,T52	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T383,T397,T280	Yes	T383,T397,T280	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T72,T73	Yes	T52,T53,T54	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T383,T397,T280	Yes	T383,T397,T52	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T59,T72,T73	Yes	T59,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T280,*T398,*T399	Yes	T383,T397,T280	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T383,T397,T52	Yes	T383,T397,T52	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T64,T156,T210	Yes	T64,T156,T210	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T2,*T50,*T76	Yes	T2,T50,T75	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T15,T193,T197	Yes	T15,T193,T197	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T13,*T209,*T14	Yes	T13,T209,T14	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T13,T209,T14	Yes	T13,T209,T14	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T209,T52,T151	Yes	T209,T52,T151	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T209,T52,T151	Yes	T209,T52,T151	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T209,T52,T151	Yes	T209,T52,T151	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T209,T52,T151	Yes	T209,T52,T151	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T209,T52,T151	Yes	T209,T52,T151	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T209,T52,T151	Yes	T209,T52,T151	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T209,T52,T151	Yes	T209,T52,T151	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T209,T52,T151	Yes	T209,T52,T151	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T209,T151,T51	Yes	T209,T151,T51	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T209,T151,T51	Yes	T209,T52,T151	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T209,T151,T51	Yes	T209,T151,T51	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T209,*T151,*T51	Yes	T209,T151,T51	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T209,T52,T151	Yes	T209,T52,T151	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T19,T209,T20	Yes	T19,T209,T20	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	INPUT
tl_usbdev_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T19,*T245,*T209	Yes	T19,T245,T209	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T19,T245,T209	Yes	T19,T245,T209	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T35	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T4,T35	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T249,T250,T251	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T35	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T3,T256,T395	Yes	T3,T256,T395	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T256,T395	Yes	T3,T256,T395	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T3,T35,T83	Yes	T3,T35,T83	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T3,T256,T395	Yes	T3,T256,T395	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T3,T35,T83	Yes	T3,T35,T83	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T3,T395,T306	Yes	T3,T395,T306	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T3,T35,T83	Yes	T3,T35,T83	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T3,T35,T83	Yes	T3,T35,T83	INPUT
tl_hmac_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T3,T35,T83	Yes	T3,T35,T83	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T35,T83	Yes	T3,T35,T83	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T3,T256,T395	Yes	T3,T256,T395	INPUT
tl_hmac_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T3,*T256,*T395	Yes	T3,T256,T395	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T3,T35,T83	Yes	T3,T35,T83	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T123,T270,T457	Yes	T123,T270,T457	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T123,T270,T457	Yes	T123,T270,T457	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T51,*T72,*T73	Yes	T51,T72,T73	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T270,T457,T458	Yes	T270,T457,T458	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	INPUT
tl_kmac_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T83,T123,T174	Yes	T83,T123,T174	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T83,T123,T174	Yes	T83,T123,T174	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T123,T111,T166	Yes	T270,T457,T458	INPUT
tl_kmac_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T51,*T72,*T73	Yes	T51,T72,T73	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T123,*T111,*T166	Yes	T270,T457,T458	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T83,T123,T174	Yes	T83,T123,T174	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T632,T111,T663	Yes	T632,T111,T663	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T632,T111,T663	Yes	T632,T111,T663	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T35,T83,T632	Yes	T35,T83,T632	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T632,T111,T663	Yes	T632,T111,T663	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T35,T83,T632	Yes	T35,T83,T632	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T77,*T72,*T73	Yes	T77,T72,T73	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T35,T83,T632	Yes	T35,T83,T632	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T35,T632,T111	Yes	T35,T632,T111	INPUT
tl_aes_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T35,T632,T111	Yes	T35,T632,T111	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T632,T111,T663	Yes	T632,T111,T663	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T35,T632,T663	Yes	T35,T632,T111	INPUT
tl_aes_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T77,*T72,*T73	Yes	T77,T72,T73	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T35,*T632,*T111	Yes	T35,T632,T111	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T35,T632,T111	Yes	T35,T632,T111	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T123,*T111,*T256	Yes	T123,T111,T256	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T123,T632,T111	Yes	T123,T632,T111	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T77,*T72,*T73	Yes	T77,T72,T73	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T123,T632,T111	Yes	T123,T632,T111	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T77,*T72,*T73	Yes	T77,T72,T73	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T123,*T632,*T111	Yes	T123,T632,T111	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T123,T632,T111	Yes	T123,T632,T111	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T123,T632,T111	Yes	T123,T632,T111	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T123,T632,T111	Yes	T123,T632,T111	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T123,*T632,*T111	Yes	T123,T632,T111	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	INPUT
tl_edn1_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	INPUT
tl_edn1_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T123,*T111,*T256	Yes	T123,T111,T256	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T123,T111,T256	Yes	T123,T111,T256	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T123,T111,T121	Yes	T123,T111,T121	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T123,T111,T121	Yes	T123,T111,T121	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T76,*T51,*T198	Yes	T76,T51,T198	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	INPUT
tl_otbn_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T123,T111,T121	Yes	T123,T111,T121	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	INPUT
tl_otbn_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T76,*T51,*T198	Yes	T76,T51,T198	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T123,*T111,*T121	Yes	T123,T111,T121	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T35,T83,T123	Yes	T35,T83,T123	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	INPUT
tl_keymgr_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T123,*T111,*T49	Yes	T123,T111,T49	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T123,T111,T49	Yes	T123,T111,T49	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T2,*T259,*T59	Yes	T2,T259,T59	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T59,T72,T73	Yes	T59,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T59,*T72,*T73	Yes	T2,T259,T59	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T47	Yes	T1,T2,T47	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T443	Yes	T1,T2,T443	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T443	Yes	T1,T2,T443	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T1,T2,T47	Yes	T1,T2,T47	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T443	Yes	T1,T2,T443	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T75,*T51,*T77	Yes	T75,T51,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T1,T2,T443	Yes	T1,T2,T443	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T1,T2,T443	Yes	T1,T2,T443	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T178,T51,T311	Yes	T178,T51,T311	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T44,T113	Yes	T1,T2,T47	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T1,T44,T113	Yes	T1,T2,T47	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T75,T51,T77	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T1,*T113,*T175	Yes	T1,T443,T242	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T1,T2,T443	Yes	T1,T2,T443	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range