Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T64,T156,T210	Yes	T64,T156,T210	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T2,*T50,*T76	Yes	T2,T50,T75	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T2,T49,T68	Yes	T2,T49,T68	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T2,T49,T68	Yes	T2,T49,T68	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T2,T49,T68	Yes	T2,T49,T68	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T2,T47,T97	Yes	T2,T47,T97	INPUT
tl_uart0_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T47,T97,T48	Yes	T47,T97,T48	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T47,T97	Yes	T2,T47,T97	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T2,T47,T97	Yes	T2,T47,T97	INPUT
tl_uart0_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T259,*T673,*T72	Yes	T259,T673,T72	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T2,*T47,*T97	Yes	T2,T47,T97	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T2,T47,T97	Yes	T2,T47,T97	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	INPUT
tl_uart1_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	INPUT
tl_uart1_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T99,*T102,*T337	Yes	T99,T102,T337	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T99,T102,T337	Yes	T99,T102,T337	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	INPUT
tl_uart2_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	INPUT
tl_uart2_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T8,*T144,*T329	Yes	T8,T144,T329	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T8,T144,T329	Yes	T8,T144,T329	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	INPUT
tl_uart3_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	INPUT
tl_uart3_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T16,*T18,*T317	Yes	T16,T18,T317	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T16,T18,T317	Yes	T16,T18,T317	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T209,T256,T212	Yes	T209,T256,T212	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T209,T256,T212	Yes	T209,T256,T212	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T209,T256,T212	Yes	T209,T256,T212	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T209,T256,T212	Yes	T209,T256,T212	INPUT
tl_i2c0_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T256,T212,T321	Yes	T256,T212,T321	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T209,T256,T212	Yes	T209,T256,T212	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T209,T256,T212	Yes	T209,T256,T212	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T209,*T256,*T212	Yes	T209,T256,T212	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T209,T256,T212	Yes	T209,T256,T212	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T209,T256,T330	Yes	T209,T256,T330	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T209,T256,T330	Yes	T209,T256,T330	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T209,T256,T330	Yes	T209,T256,T330	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T209,T256,T330	Yes	T209,T256,T330	INPUT
tl_i2c1_i.d_error	Yes	Yes	T72,T73,T249	Yes	T72,T73,T249	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T256,T330,T316	Yes	T256,T330,T316	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T209,T256,T330	Yes	T209,T256,T330	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T209,T256,T330	Yes	T209,T256,T330	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T209,*T256,*T330	Yes	T209,T256,T330	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T209,T256,T330	Yes	T209,T256,T330	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T209,T256,T339	Yes	T209,T256,T339	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T209,T256,T339	Yes	T209,T256,T339	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T209,T256,T339	Yes	T209,T256,T339	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T209,T256,T339	Yes	T209,T256,T339	INPUT
tl_i2c2_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T256,T339,T316	Yes	T256,T339,T316	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T209,T256,T339	Yes	T209,T256,T339	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T209,T256,T339	Yes	T209,T256,T339	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T209,*T256,*T339	Yes	T209,T256,T339	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T209,T256,T339	Yes	T209,T256,T339	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T213,T351,T151	Yes	T213,T351,T151	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T213,T351,T151	Yes	T213,T351,T151	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T213,T351,T52	Yes	T213,T351,T52	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T213,T351,T52	Yes	T213,T351,T52	INPUT
tl_pattgen_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T213,T351,T151	Yes	T213,T351,T151	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T213,T351,T151	Yes	T213,T351,T52	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T213,T351,T151	Yes	T213,T351,T52	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T51,T72,*T73	Yes	T51,T72,T73	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T213,*T351,*T151	Yes	T213,T351,T151	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T213,T351,T52	Yes	T213,T351,T52	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T214,T215,T145	Yes	T214,T215,T145	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T214,T215,T145	Yes	T214,T215,T145	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T214,T215,T145	Yes	T214,T215,T145	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T214,T215,T145	Yes	T214,T215,T145	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T214,T215,T145	Yes	T214,T215,T145	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T214,T215,T145	Yes	T214,T215,T145	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T214,T215,T145	Yes	T214,T215,T145	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T59,*T72,*T73	Yes	T59,T72,T73	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T214,*T215,*T145	Yes	T214,T215,T145	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T214,T215,T145	Yes	T214,T215,T145	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T256,T17,T55	Yes	T256,T17,T55	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T256,T17,T55	Yes	T256,T17,T55	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T256,T17,T55	Yes	T256,T17,T55	INPUT
tl_gpio_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T35	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T8,T209,T50	Yes	T8,T209,T50	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T8,T209,T50	Yes	T8,T209,T50	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T8,T209,T50	Yes	T8,T209,T50	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T8,T209,T50	Yes	T8,T209,T50	INPUT
tl_spi_device_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T8,T209,T50	Yes	T8,T209,T50	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T209,T50	Yes	T8,T209,T50	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T8,T209,T50	Yes	T8,T209,T50	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T8,*T209,*T50	Yes	T8,T209,T50	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T8,T209,T50	Yes	T8,T209,T50	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T674,T675,T145	Yes	T674,T675,T145	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T674,T675,T145	Yes	T674,T675,T145	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T674,T675,T145	Yes	T674,T675,T145	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T674,T675,T145	Yes	T674,T675,T145	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T674,T675,T676	Yes	T674,T675,T676	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T674,T675,T145	Yes	T674,T675,T145	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T674,T675,T145	Yes	T674,T675,T145	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T674,*T675,*T145	Yes	T674,T675,T145	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T674,T675,T145	Yes	T674,T675,T145	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T35,T83	Yes	T2,T35,T83	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T35,T83,T5	Yes	T35,T83,T5	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T2,T35,T83	Yes	T2,T35,T83	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T2,T35,T83	Yes	T2,T35,T83	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T35,T83,T5	Yes	T35,T83,T5	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T35,T83,T5	Yes	T2,T35,T83	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T35,T83,T5	Yes	T2,T35,T83	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T59,*T72,*T73	Yes	T59,T72,T73	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T35,*T83,*T5	Yes	T35,T83,T5	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T2,T35,T83	Yes	T2,T35,T83	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T4,T35	Yes	T1,T3,T4	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T59,*T72,*T73	Yes	T59,T72,T73	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T35,T83,T8	Yes	T35,T83,T8	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T35,T83,T6	Yes	T35,T83,T6	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T8,T144,T323	Yes	T8,T144,T323	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T77,*T72,*T73	Yes	T668,T669,T77	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T35,*T83,*T8	Yes	T35,T83,T8	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T51,*T59,*T72	Yes	T51,T59,T72	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T50,*T149,*T51	Yes	T50,T149,T51	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T150,*T123,*T111	Yes	T150,T123,T111	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T51,T72,T73	Yes	T51,T72,T73	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T51,T72,T73	Yes	T51,T72,T73	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T51,T72,T73	Yes	T51,T72,T73	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T35	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T51,T72,T73	Yes	T51,T72,T73	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T72,T73	Yes	T51,T72,T73	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T35	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T51,T72,T73	Yes	T51,T72,T73	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T4,T35	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T51,T72,T73	Yes	T51,T72,T73	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T8,T150,T165	Yes	T8,T150,T165	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T8,T150,T165	Yes	T8,T150,T165	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T8,T150,T165	Yes	T8,T150,T165	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T8,T150,T165	Yes	T8,T150,T165	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T8,T50,T47	Yes	T8,T150,T165	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T114,T168,T313	Yes	T114,T168,T313	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T8,T150,T50	Yes	T8,T150,T165	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T51,*T314,*T315	Yes	T51,T314,T315	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T8,*T50,*T44	Yes	T8,T150,T165	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T8,T150,T165	Yes	T8,T150,T165	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T125,T20,T101	Yes	T125,T20,T101	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T125,T20,T101	Yes	T125,T20,T101	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T4,T35	Yes	T1,T3,T4	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T35	Yes	T1,T3,T4	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T64	Yes	T4,T5,T64	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T4,T5,T64	Yes	T4,T5,T64	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T4,T5,T64	Yes	T4,T5,T64	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T4,T5,T64	Yes	T4,T5,T64	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T64	Yes	T4,T5,T64	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T64	Yes	T4,T5,T64	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T4,T5,T64	Yes	T4,T5,T64	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T77,*T72,*T73	Yes	T77,T72,T73	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T64	Yes	T4,T5,T64	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T4,T5,T64	Yes	T4,T5,T64	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T443,T47	Yes	T1,T443,T47	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T1,T443,T47	Yes	T1,T443,T47	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T1,T443,T47	Yes	T1,T443,T47	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T1,T443,T47	Yes	T1,T443,T47	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T1,T113,T175	Yes	T1,T113,T175	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T44,T113	Yes	T1,T47,T48	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T1,T44,T113	Yes	T1,T47,T48	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T1,*T113,*T175	Yes	T1,T443,T113	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T1,T443,T47	Yes	T1,T443,T47	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T35	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T35	Yes	T1,T4,T35	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T2,*T76,*T259	Yes	T2,T76,T259	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T4,T35	Yes	T2,T4,T35	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T2,T4,T35	Yes	T2,T4,T35	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T2,T4,T35	Yes	T2,T4,T35	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T2,T4,T35	Yes	T2,T4,T35	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T35,T83	Yes	T4,T35,T83	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T35,T83	Yes	T2,T4,T35	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T35,T83	Yes	T2,T4,T35	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T77,*T72,*T73	Yes	T2,T75,T670	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T35,*T83	Yes	T4,T35,T83	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T2,T4,T35	Yes	T2,T4,T35	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T20,T69,T190	Yes	T20,T69,T190	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T20,T69,T190	Yes	T20,T69,T190	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T20,T69,T190	Yes	T20,T69,T190	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T20,T69,T190	Yes	T20,T69,T190	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T20,T69,T257	Yes	T20,T69,T257	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T190,T257	Yes	T20,T69,T190	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T190,T257,T465	Yes	T20,T69,T190	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T51,*T77,*T72	Yes	T51,T77,T72	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T20,*T69,*T257	Yes	T20,T69,T190	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T20,T69,T190	Yes	T20,T69,T190	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T107,T256,T20	Yes	T107,T256,T20	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T107,T256,T20	Yes	T107,T256,T20	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T107,T256,T20	Yes	T107,T256,T20	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T107,T256,T20	Yes	T107,T256,T20	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T107,T256,T20	Yes	T107,T256,T20	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T107,T256,T20	Yes	T107,T256,T20	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T107,T20,T190	Yes	T107,T256,T20	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T77,*T72,*T73	Yes	T77,T72,T73	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T107,*T256,*T20	Yes	T107,T256,T20	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T107,T256,T20	Yes	T107,T256,T20	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T2,*T50,*T75	Yes	T2,T50,T75	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T76,T51,T77	Yes	T76,T51,T77	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T4,T35	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range