Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149111	1			T72	16		T73	5		T74	153
values[2]	10695	1			T72	1		T74	5		T456	1
values[3]	4330	1			T520	1		T467	1		T532	66
values[4]	2598	1			T520	1		T532	21		T438	5
values[5]	1688	1			T520	1		T532	1		T438	10
values[6]	1062	1			T520	1		T438	5		T442	13
values[7]	692	1			T520	1		T438	8		T442	7
values[8]	495	1			T520	1		T438	3		T442	5
values[9]	379	1			T520	1		T438	1		T442	10
values[10]	356	1			T520	1		T442	4		T435	9
values[11]	277	1			T520	1		T442	10		T435	12
values[12]	203	1			T520	1		T442	8		T435	5
values[13]	213	1			T520	1		T442	12		T435	5
values[14]	180	1			T520	1		T442	9		T435	5
values[15]	208	1			T520	1		T442	8		T435	3
values[16]	189	1			T520	1		T442	6		T435	7
values[17]	177	1			T520	1		T442	7		T435	6
values[18]	189	1			T520	1		T442	9		T435	11
values[19]	187	1			T520	1		T442	4		T435	6
values[20]	194	1			T520	1		T442	10		T435	9
values[21]	193	1			T520	1		T442	6		T435	7
values[22]	206	1			T520	1		T442	15		T435	14
values[23]	172	1			T520	2		T442	4		T435	9
values[24]	142	1			T520	1		T442	3		T435	3
values[25]	179	1			T520	1		T442	17		T435	10
values[26]	195	1			T520	1		T442	4		T435	8
values[27]	213	1			T520	1		T442	18		T435	9
values[28]	155	1			T520	1		T442	2		T435	8
values[29]	146	1			T520	1		T442	3		T435	3
values[30]	158	1			T520	1		T442	5		T435	4
values[31]	214	1			T520	1		T442	3		T435	4
values[32]	155	1			T520	1		T442	4		T435	5
values[33]	169	1			T520	1		T442	15		T435	10
values[34]	153	1			T520	1		T442	8		T435	5
values[35]	168	1			T520	1		T442	19		T435	11
values[36]	144	1			T520	1		T442	8		T435	4
values[37]	178	1			T520	1		T442	5		T435	8
values[38]	186	1			T520	1		T442	14		T435	6
values[39]	156	1			T520	1		T442	9		T435	4
values[40]	168	1			T520	1		T442	6		T435	6
values[41]	174	1			T520	1		T442	7		T435	8
values[42]	197	1			T520	1		T442	3		T435	7
values[43]	144	1			T520	1		T442	7		T435	3
values[44]	191	1			T520	1		T442	7		T435	5
values[45]	206	1			T520	1		T442	11		T435	14
values[46]	183	1			T520	1		T442	4		T435	21
values[47]	194	1			T520	1		T442	3		T435	26
values[48]	185	1			T520	1		T442	19		T435	3
values[49]	169	1			T520	1		T442	10		T435	5
values[50]	194	1			T520	1		T442	7		T435	3
values[51]	179	1			T520	1		T442	12		T435	4
values[52]	161	1			T520	1		T442	8		T435	5
values[53]	155	1			T520	1		T442	17		T435	4
values[54]	216	1			T520	1		T442	7		T435	4
values[55]	157	1			T520	1		T442	6		T435	7
values[56]	158	1			T520	1		T442	11		T435	5
values[57]	163	1			T520	1		T442	11		T435	19
values[58]	124	1			T520	1		T442	3		T435	7
values[59]	152	1			T520	1		T442	11		T435	5
values[60]	149	1			T520	1		T442	4		T435	5
values[61]	113	1			T520	1		T442	7		T435	3
values[62]	102	1			T520	1		T442	4		T435	5
values[63]	131	1			T520	1		T435	10		T629	14
values[64]	104	1			T520	1		T435	7		T629	6
values[65]	110	1			T520	1		T435	9		T629	4
values[66]	100	1			T520	1		T435	5		T629	4
values[67]	97	1			T520	1		T435	6		T629	4
values[68]	93	1			T520	1		T435	5		T629	8
values[69]	121	1			T520	1		T435	3		T629	10
values[70]	111	1			T520	1		T435	5		T629	5
values[71]	98	1			T520	1		T435	3		T629	5
values[72]	99	1			T520	1		T435	6		T629	7
values[73]	94	1			T520	1		T629	5		T505	1
values[74]	88	1			T520	1		T629	5		T505	1
values[75]	96	1			T520	1		T629	4		T505	1
values[76]	108	1			T520	1		T629	3		T505	1
values[77]	98	1			T520	1		T629	2		T505	1
values[78]	76	1			T520	1		T629	7		T505	1
values[79]	60	1			T520	1		T629	6		T505	1
values[80]	60	1			T520	1		T629	2		T505	1
values[81]	57	1			T520	1		T505	1		T832	1
values[82]	52	1			T520	1		T505	1		T832	1
values[83]	54	1			T520	1		T505	1		T832	1
values[84]	48	1			T520	1		T505	1		T832	1
values[85]	48	1			T520	1		T505	2		T832	1
values[86]	58	1			T520	1		T505	1		T832	1
values[87]	65	1			T520	1		T505	1		T832	1
values[88]	49	1			T520	1		T505	1		T832	1
values[89]	62	1			T520	1		T505	1		T832	1
values[90]	48	1			T520	1		T505	1		T832	1
values[91]	59	1			T520	1		T505	1		T832	1
values[92]	60	1			T520	1		T505	1		T832	1
values[93]	65	1			T520	1		T505	1		T832	1
values[94]	60	1			T520	1		T505	1		T832	1
values[95]	63	1			T520	1		T505	1		T832	1
values[96]	52	1			T520	1		T505	1		T832	1
values[97]	71	1			T520	1		T505	1		T832	1
values[98]	74	1			T520	1		T505	1		T832	1
values[99]	77	1			T520	1		T505	1		T832	2
values[100]	57	1			T520	1		T505	1		T832	1
values[101]	52	1			T520	1		T505	1		T832	1
values[102]	66	1			T520	1		T505	1		T832	1
values[103]	51	1			T520	1		T505	1		T832	1
values[104]	50	1			T520	2		T505	1		T832	1
values[105]	61	1			T520	1		T505	1		T832	1
values[106]	61	1			T520	1		T505	1		T832	1
values[107]	45	1			T520	3		T505	1		T832	2
values[108]	53	1			T520	11		T505	1		T832	1
values[109]	65	1			T520	1		T505	1		T832	1
values[110]	58	1			T520	1		T505	1		T832	2
values[111]	70	1			T520	5		T505	1		T832	1
values[112]	60	1			T520	4		T505	1		T832	1
values[113]	47	1			T520	1		T505	1		T832	2
values[114]	84	1			T520	3		T505	1		T832	12
values[115]	61	1			T520	1		T505	2		T832	1
values[116]	67	1			T520	2		T505	2		T832	1
values[117]	55	1			T520	1		T505	1		T832	2
values[118]	60	1			T520	3		T505	1		T832	2
values[119]	63	1			T520	2		T505	1		T832	1
values[120]	45	1			T520	2		T505	2		T832	1
values[121]	40	1			T520	2		T505	1		T832	1
values[122]	59	1			T520	3		T505	4		T832	1
values[123]	52	1			T520	1		T505	4		T832	2
values[124]	50	1			T520	1		T505	1		T832	1
values[125]	69	1			T520	3		T505	2		T832	1
values[126]	95	1			T520	1		T505	1		T832	2
values[127]	753	1			T520	38		T505	39		T832	32
values[128]	6299	1			T520	262		T505	409		T832	381